# Difference between the two coding styles for clock gating

1. ## Difference between the two coding styles for clock gating

Hi all,

I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried

Method 1 : where i explicitly coarse & fine gater
```Code Verilog - [expand]1
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always @(posedge clk) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5] & coarse_en)
mem[i][0] <= mem_d [i][0]
end
end```

Method 2 : where it's implicit and gating
```Code Verilog - [expand]1
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always @(posedge clk) begin
if (coarse_en) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5])
mem[i][0] <= mem_d [i][0]
end
end
end```

Method 2 shows power saving but method 1 doesn't. Why do I see the difference ?

~rahdirs

- - - Updated - - -

Originally Posted by rahdirs
Method 1 : where i explicitly coarse & fine gater
```Code Verilog - [expand]1
2
3
4
5
6
always @(posedge clk) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5] & coarse_en)
mem[i][0] <= mem_d [i][0]
end
end```
I think I've figured it out. It wasn't showing savings probably because I was using the bit-wise and (&) instead of the logical and (&&) ? Will try with this change

•

2. ## Re: Difference between the two coding styles for clock gating

Originally Posted by rahdirs
Hi all,

I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried

Method 1 : where i explicitly coarse & fine gater
```Code Verilog - [expand]1
2
3
4
5
6
always @(posedge clk) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5] & coarse_en)
mem[i][0] <= mem_d [i][0]
end
end```

Method 2 : where it's implicit and gating
```Code Verilog - [expand]1
2
3
4
5
6
7
8
always @(posedge clk) begin
if (coarse_en) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5])
mem[i][0] <= mem_d [i][0]
end
end
end```

Method 2 shows power saving but method 1 doesn't. Why do I see the difference ?

~rahdirs

- - - Updated - - -

I think I've figured it out. It wasn't showing savings probably because I was using the bit-wise and (&) instead of the logical and (&&) ? Will try with this change
I think you have stumbled upon the problem of shared enable detection. The coding style of method 2 might be easier for some tools to pick.

•

3. ## Re: Difference between the two coding styles for clock gating

Method 2 should use flip-flop enable, and thus spend less logic.

Method 1 probably will use more logic to implement the (we[i>>5] && coarse_en) part. In this case coarse_en should not be part of flip-flop enable, but part of LUT logic.

Also, maybe if you make your for loop increment by 16, instead increment by 1 and shifting, you might save some logic and increase speed.

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