Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to measure Chip size using SVRF for calibre DRC

Status
Not open for further replies.

sam88

Newbie level 2
Joined
Dec 7, 2017
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
14
I want to measure chip size for DRC purpose.
How can I measure if my layout is > 3mmx3mm or < 3mm x 3mm using SVRF commands for DRC

Please help.
Thanks
sam
 

If you are aware of SVRF (Calibre) code then you can use top level Boundary layer as input parameter, use ANGLE command to get the horizontal and vertical edges, report the length of horizontal and vertical edges either by using LENGTH > 0, this would report coordinates of failing edge and then you can measure the difference between coordinates.

Another approach is use DFM command.
 

EXTENT command givers you a bounding box (rectangle) for the whole design (all layers).
I don't know the command to measure the sides of a rectangle - but this should be pretty basic in SVRF.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top