What's the difference in this two gain boosted structure,why results differ so much.

To verify the gain boosted, I design this easily to understand models which are as follows.
Fig.1 is the common gate amplify structure,

Input source is bottom voltage source V19 which has AC and DC signal shown below

Both two transistors are in saturation region and I add an inductor with inductance of 10PH to treat as an AC block in order to investigate the maximum gain the transistors can give.
Gain boosted structure is realized by a ideal amplifying structure, with the parameters showm below

This gain parameter will vary from 10 to 10K to test the boosted outcomes.
Plus input and reference output are set to make sure the two transistors are operating in a saturation situations.
Sweeping the gain of gain booster amplifier, the outcomes are


However, I design an similar structure which is common gate amplifier, which is shown below.

Input source in V24, with AC magnitude 1V, and the current sink is to make sure the gain boosted amplifier will not deterioate the operating point of main MOS NM6, the current is 44.6uA. Other conditions are the same, the outcomes are


I think the outcomes should follow the same rountine: the higher the gain of gain booster, the higher the whole gain, why these two are different and the first one reaches an upper boundary. I really do not know why the up limit exists in the first one.

Thank you.

I assume that OPAmp has a verilogA model with default gain bandwidth and other parameters which you didn't modify. The default is probably not enough high, so I would try to play some with the freq_unitygain parameter. If you increase that probably the gain of your first circuit will increase, however I am not sure this is the only thing. It would be better I think if you would connect a simple VCVS from analogLib, more clear how it works, in the verilogA model I don't trust.
At the bottom circuit you used a voltage source to drive the input, this is not comparable I think with the upper case, where is a transconductance. Use VCCS from analogLib to drive bottom circuit, for better comparison.

frankrose said:

I assume that OPAmp has a verilogA model with default gain bandwidth and other parameters which you didn't modify. The default is probably not enough high, so I would try to play some with the freq_unitygain parameter. If you increase that probably the gain of your first circuit will increase, however I am not sure this is the only thing. It would be better I think if you would connect a simple VCVS from analogLib, more clear how it works, in the verilogA model I don't trust.
At the bottom circuit you used a voltage source to drive the input, this is not comparable I think with the upper case, where is a transconductance. Use VCCS from analogLib to drive bottom circuit, for better comparison.

Click to expand...

Thanks for reply, I‘ve tried,and I think the default parameters do not affect the performance. This is because the input impedance looking into source is 1/gm which is 2.2K,smaller than the input impedance of amplifier model, bandwidth may affect the time characterists,but may not affect the ac response, especially near DC and low frequency. I still can not find the reason.8-O

Here is my guess:
The gain boosting enhances the Rds only, but at the drain there are other conductance, like the reverse biased drain-bulk diode's loss. The breakdown voltage of this diode is not too high, so relatively at higher drain voltages the loss of this device can be comparable with your enhanced Rds probably. So you can increase the Rds by gain-boosting, but over a value the other parasitic conductance dominates and determines Rout and the gain.
Try to decrease the Vds of your device, thus the parasitic drain-bulk diode's dynamic resistance will increase.
(However at too low Vds values the gds of your device can arise.)