I have few questions regarding coefficients of Type-3 Digital PLL

1) Why must k3 < k2 < k1 < 1 ?

2) Why is there no coefficient tolerance problem in a digital implementation ? And does complex zeroes actually give rise to ringing phenomenon in digital implementation ? Could anyone give an actual, empirical demo example with regards to a working digital PLL ?

3) Are there any simple ways to derive these three coefficients value for robust solution ? I heard we could do it with a matrix solution : state[n+1] = A*state[n] Have anyone used such matrix solution ? Could anyone elaborate more about this ?

4) Could anyone cross reference these attenuation coefficients to analog circuit domain for better overall understanding ?

Note: Screenshot taken from Floyd Gardner book "Phaselock Techniques 3rd edition" page 69