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    Clock Gaters Tree -> routing conjection

    Hi All,

    Please see below the tree structures of the Clock Gaters in FPGA.

    There is a PLL, several Center Gaters (controlled by SW), and many hierarchies with local Clock Gaters, which are controlled by Internal Logic.

    The problem is so that the lines, which are shown in RED, take a lot of routing resources. The Global Lines could not be taken in account since they are used for another purposes.

    So, what's the solution in order to reduce the routing resources? Keeping two hierarchies for clock gating is MUST(the first hierarchy is for SW Clock Control, the second hierarchy is for Logic Clock Control).

    Click image for larger version. 

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    Thank you!

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    Re: Clock Gaters Tree -> routing conjection

    Why are you gating the clock?
    And when you do gate a clock, using the global buffers is a must, otherwise your routing will die, as you have discovered, and the clocks will just be terrible and have lots of skew.

    This seems like a massive bad idea.


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    Re: Clock Gaters Tree -> routing conjection

    Why are you gating the clock? " - this FPGA is a prototype for ASIC. So, in ASIC there are a lot of gated clocks. The point is so some of them are functional (not just for power reduction). So, I cannot change an architecture of the gated clock tree...
    Should I manually insert a global buffer for the gated clock? What should I do for 1000 gated clocks? Can I use so many Global Buffers?
    Does the Global Buffer route a signal to a Global Line (low skew line)?
    What's the solution for 1000 gated clocks? There are no so many Global Lines in the device...



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    Re: Clock Gaters Tree -> routing conjection

    I have done little ASIC work, and no prototyping, but the ASIC I did work on clock gating was frowned upon and not allowed. I know it is pervasive in ASIC design though. We mostly stuck to standard FPGA style coding for the main logic, but there may have been gating in the peripherals I was not involved in. But 1000 gated clocks seems rather excessive. Are you trying to individually turn on and off 1000 modules? why so many?
    Is this company work or hobby project? If for a company, dont you have someone with the correct expertise? I know there are techniques for converting gated clocks in FPGAs from reading posts at Altera and Xilinx forums - but thats the best I can do.



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    Re: Clock Gaters Tree -> routing conjection

    The FPGA (as ASIC) is intended to be low power, so they use a switch during the RTL compilation, which inserts automatic gated clock instead of enables for data. The technique is to convert the Enable logic for Data to Enable logic for Clock Gator. So, theoretically as many flops with data enables, as many clock gators ...

    Again does the Global Buffer routes the signal to Global Line (Low Skew Line)? Are you about BUFG or BUFGE (Xilinx)?

    You wrote: "I know there are techniques for converting gated clocks in FPGAs". Do you mean a technique for convertion gated clock to what? to enables/selectors for data muxes? probably can you point to some relevant materials?



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    Re: Clock Gaters Tree -> routing conjection




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    Re: Clock Gaters Tree -> routing conjection

    The largest ultrascale devices have <500 BUFGs
    But gated clocks will not necessarily be promoted to a global driver. For altera, resets with a high fanout will get promoted, as will clocks, but you often have to promote them manually.

    You need to investigate the automatic gate conversion.



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    Re: Clock Gaters Tree -> routing conjection

    I can speak a little for xilinx.

    See this, page 59 - https://www.xilinx.com/support/docum...s_Clocking.pdf

    There are special clock buffers for clock gating. I guess you have to insert them manually before FPGA prototyping. I have never done such work.
    FPGA enthusiast!



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    Re: Clock Gaters Tree -> routing conjection

    This is why those ASIC emulation tools that worked in conjunction with the ASIC emulation boards and mainframes existed.

    Haven't looked at these recently, but back a half dozen years ago they handled the translation of gated clocks into FPGAs along with the partitioning of the ASIC design across multiple FPGAs. If you are doing this port manually you'll have to come up with your own solution to this conversion.



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