akram149
Newbie level 4
HI all,
we are trying to interface custom MAC controller with GMII interface with SGMII ip core in SGMII mode and it is connected to Ethernet phy on the custom board we are using VCU118 fpga.
we have enabled management interface, external management interface and also auto-negotiation. SGMII PHY mode is off.
we are able to access Ethernet phy registers via MDIO but when we are trying to access SGMII IP core management registers we are not getting any response.
we kept phy address as 5'b10000.
following is the snippet of connections
please suggest any changes in the connections or i am missing something.
Thanks
we are trying to interface custom MAC controller with GMII interface with SGMII ip core in SGMII mode and it is connected to Ethernet phy on the custom board we are using VCU118 fpga.
we have enabled management interface, external management interface and also auto-negotiation. SGMII PHY mode is off.
we are able to access Ethernet phy registers via MDIO but when we are trying to access SGMII IP core management registers we are not getting any response.
we kept phy address as 5'b10000.
following is the snippet of connections
Code:
GMII_Block_PMA_0_wrapper GMII_Interface_GEM0_inst(
.independent_clock_bufg_0 (independent_clock_200),
.gtpowergood_0 (gtpowergood_0_out),
.gtrefclk_in_0_clk_n (gtrefclk_in_0_clk_n_in), // Differential -ve of reference clock for MGT: very high quality.
.gtrefclk_in_0_clk_p (gtrefclk_in_0_clk_p_in), // Differential +ve of reference clock for MGT: very high quality.
.gtrefclk_out_0 (),
.sgmii_0_rxn (sgmii_0_rxn_in), // Differential -ve for serial reception from PMD to PMA.
.sgmii_0_rxp (sgmii_0_rxp_in), // Differential +ve for serial reception from PMD to PMA.
.sgmii_0_txn (sgmii_0_txn_out), // Differential -ve of serial transmission from PMA to PMD.
.sgmii_0_txp (sgmii_0_txp_out), // Differential +ve of serial transmission from PMA to PMD.
.gmii_isolate_0 (),
.gmii_pcs_pma_0_rx_dv (fab_mac0_rx_dv_sync),
.gmii_pcs_pma_0_rx_er (fab_mac0_rx_er_sync),
.gmii_pcs_pma_0_rxd (fab_mac0_rxd_sync),
.gmii_pcs_pma_0_tx_en (fab_mac0_tx_en_sync),
.gmii_pcs_pma_0_tx_er (fab_mac0_tx_er_sync),
.gmii_pcs_pma_0_txd (fab_mac0_txd_sync),
// .sgmii_rx_clk (sgmii_rx_clk),
// .sgmii_clk (sgmii_clk),
.sgmii_clk_en_0 (sgmii_clk_en_0),
.sgmii_clk_f_0 (sgmii_clk_f_0),
.sgmii_clk_r_0 (sgmii_clk_r_0), // going to mac tx clk
.sgmii_rx_clk_en_0 (sgmii_rx_clk_en_0),
.sgmii_rx_clk_f_0 (sgmii_rx_clk_f_0),
.sgmii_rx_clk_r_0 (sgmii_rx_clk_r_0), // going to mac rx clk
.mdc_0 (fab_mdio0_mdc_h2f), // from GEM
.mdio_i_0 (fab_mdio0_out_h2f),
.mdio_o_0 (fab_mdio0_in_f2h),
.mdio_t_0 (),
.mdio_t_in_0 (fab_mdio0_oe_h2f), // check important going to ext_t_in
// .mdio_pcs_pma_0_mdio_io (mdio_from_gem), // from GEM
.phyaddr_0 (5'b10000),
.ext_mdc_0 (phy_mdc), // clk to external phy
.ext_mdio_i_0 (ext_mdio_i_0),
.ext_mdio_o_0 (ext_mdio_o_0),
.ext_mdio_t_0 (ext_mdio_t_0),
// .ext_mdio_pcs_pma_0_mdio_io (phy_mdio), // mdio to external phy
.configuration_valid_0 (1'b0),
.configuration_vector_0 (5'b00000),
.an_adv_config_val_0 (1'b0),
.an_adv_config_vector_0 (16'h0000),
.an_interrupt_0 (Autonegotiation_interrupt),
.an_restart_config_0 (1'b0),
.speed_is_100_0 (fab_mac0_speed_mode[0]),
.speed_is_10_100_0 (~fab_mac0_speed_mode[1]),
.signal_detect_0 (1'b1),
.reset_0 (fab_mgpio_out_h2f[1]),
.resetdone_0 (1'b1),
.status_vector_0 (status_vector_0),
.mmcm_locked_out_0 (mmcm_locked_out_0_out),
.pma_reset_out_0 (pma_reset_out_0_out),
.rxuserclk2_out_0 (rxuserclk2),
.rxuserclk_out_0 (recovered_clk),
.userclk2_out_0 (usrclk_tx), // going to gtx clk input of mac
.userclk_out_0 ()
);
IOBUF mdio ( .T(!ext_mdio_t_0), .I(ext_mdio_o_0), .O(ext_mdio_i_0), .IO(phy_mdio) );
Thanks