How can I make unmapped netlist for verilog simulation model within GTECH library?

coshy said:

Dear All,

I'm trying to make a unmapped netlist for verilog simulation within GTECH library.
But, I come across some "MULT_UNS_OP", "SELECT_OP" and \**SEQGEN**\ in the unmapped netlist by using design compiler.

Code:

ncelab: *E,CUVMUR (./syn_unmapped.v,7962|16): instance 'proc_syn.C4449' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.
  SELECT_OP C4450 ( .DATA1(pixel00), .DATA2(pixel01), .DATA3(pixel02), .DATA4(
                |
ncelab: *E,CUVMUR (./syn_unmapped.v,7987|16): instance 'proc_syn.C4450' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.
  SELECT_OP C4451 ( .DATA1(pixel00), .DATA2(pixel01), .DATA3(pixel02), .DATA4(
                |
ncelab: *E,CUVMUR (./syn_unmapped.v,8012|16): instance 'proc_syn.C4451' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.
  SELECT_OP C4452 ( .DATA1(pixel00), .DATA2(pixel01), .DATA3(pixel02), .DATA4(
                |
ncelab: *E,CUVMUR (./syn_unmapped.v,8037|16): instance 'proc_syn.C4452' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.
  SELECT_OP C4453 ( .DATA1(pixel00), .DATA2(pixel01), .DATA3(pixel02), .DATA4(
                |
ncelab: *E,CUVMUR (./syn_unmapped.v,8062|16): instance 'proc_syn.C4453' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.
  SELECT_OP C4454 ( .DATA1(pixel00), .DATA2(pixel01), .DATA3(pixel02), .DATA4(
                |
ncelab: *E,CUVMUR (./syn_unmapped.v,8087|16): instance 'proc_syn.C4454' of design unit 'SELECT_OP' is unresolved in 'worklib.proc_syn:v'.

The problem is that I can't compile the verilog simulation model(syn_unmapped.v) with GTECH library. I think GTECH library doesn't include the "MULT_UNS_OP", "SELECT_OP " in itself.

Would you please let me know what am I supposed to do to resolve this problem?

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