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Query regarding Physical design flow

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ajayg0880

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what are the consequences of minimum latency and minimum skew on design?
 

latency of what to where? are you talking about clock?
 

ajayg0880 said:
what are the consequences of minimum latency and minimum skew on design?
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Min Latency means more clock-cells, which leads to more clock-tree power.

Min skew means all the flops will switch at the same time, which will make your dynamic power to up.
 

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