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Calling VHDL code in Verilog Code

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manjunath_crl

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Dear Sir,

I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.
 

How to use those components in verilog code.
Just instantiate it as you would instantiate a Verilog module.
 

Dear Sir,

I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.

Names of the I/O ports are the same for Verilog and VHDL, just instantiate a module in your code. The tool will do the job.
 

Dear Sir,

I am calling in my program like

checkclock chekclk(.CLKA(CLK_INPUT), .GLA(FREQ1);

it is giving error as FREQ1_C not driven.

please help me solve this promlem.
 

FREQ1_C is obviously an input that you forgot to connect.
 

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