pcca
Junior Member level 3
Hello,
I am designing a low-voltage SD modulator and I am having some troubles in post-layout simulation. I have performed the layout extraction with assura (RC - decoupled capacitances) and during the simulation (spectre with APS++ in conservative mode), the output DC level of the third active-RC integrator (there are only 3 integrators in the loop filter) did not set correctly, as can be seen in the attached figure. However, to my surprise, I tried the RC extraction setting the "coupled" capacitance option and the circuit works fine (the simulation time has increased as expected).
I already checked the CMFB loop stability and cannot see any problem. All schematic simulations, including PVT corners worked. Post-layout simulations before the top-level routing also worked well with RC extraction in decoupled capacitances mode.
Has anyone ever experienced a similar issue like this?
Regards.
I am designing a low-voltage SD modulator and I am having some troubles in post-layout simulation. I have performed the layout extraction with assura (RC - decoupled capacitances) and during the simulation (spectre with APS++ in conservative mode), the output DC level of the third active-RC integrator (there are only 3 integrators in the loop filter) did not set correctly, as can be seen in the attached figure. However, to my surprise, I tried the RC extraction setting the "coupled" capacitance option and the circuit works fine (the simulation time has increased as expected).
I already checked the CMFB loop stability and cannot see any problem. All schematic simulations, including PVT corners worked. Post-layout simulations before the top-level routing also worked well with RC extraction in decoupled capacitances mode.
Has anyone ever experienced a similar issue like this?
Regards.
