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Registers in FPGA fabric

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tahirsengine

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Hi,
I am doing a project in which I need to use almost 65 registers, each one of 8 bit wide.
Now the problem is, it will consume around 15% of my FPGA distributed fabric (7 series Zynq processor).
These registers will be used for temporary data storage from some sensors.
I am using VHDL for RTL entry.
Is there any method that I can do this without spending that much space on FPGA? Actually overall space that this design is occupying is around 80% and these registers are contributing almost 15%, which I am not liking, as these buffer registers may be increased up to 200 in future expensions. And in that case I will have no other option, as other parts of the design are increasing as well.


Cheers

Tahirs
 

Would it be possible to use a BRAM instead?
But no, if you need to store data, especially for control registes, each bit needs a register. So the only way to reduce usage here is reduce the number of registers.
 

TrickyDicky said:
Would it be possible to use a BRAM instead?
But no, if you need to store data, especially for control registes, each bit needs a register. So the only way to reduce usage here is reduce the number of registers.
Click to expand...

Are there any dedicated multi-bit-registers available in FPGA fabric just like Block RAMs?
 

tahirsengine said:
Let me rephrase: Are there any dedicated multi-bit-registers available in FPGA fabric?
Click to expand...

Short answer no.
Longer answer: they would be pretty pointless, as register logic already exists. A multi-bit-register would just be the same, and allow less flexability.
 

tahirsengine said:
Let me rephrase: Are there any dedicated multi-bit-registers available in FPGA fabric?
Click to expand...

For better or worse FPGA's are quite uniform. It's an ocean of "LUTs" where LUTs are a combination of a register with logic. Most FPGA's have some number of RAMs, DSPs and big ones have SERDES but there isn't much else in terms of special functionality in there.

FPGA designers have been at this for decades and there is a reason they've chosen the LUT structure - they've found its a good compromise of logic versus register count for most applications and I suspect its not too far off the mark even for you.

For example presumably your registers are tied to actual functionality - that functionality can be implemented within the logic of the LUTs where the register resides.
 

Hello,

in such case maybe you should consider using Soft-Processor, or better the ARM CPU core from your Zynq.

Regards
 

Replacing registers by block RAM is an effective method to improve resource. You gave very little information about the structure of your design, thus we can't know if it's applicable therein.
 

asdf44 said:
For better or worse FPGA's are quite uniform. It's an ocean of "LUTs" where LUTs are a combination of a register with logic. Most FPGA's have some number of RAMs, DSPs and big ones have SERDES but there isn't much else in terms of special functionality in there.

FPGA designers have been at this for decades and there is a reason they've chosen the LUT structure - they've found its a good compromise of logic versus register count for most applications and I suspect its not too far off the mark even for you.

For example presumably your registers are tied to actual functionality - that functionality can be implemented within the logic of the LUTs where the register resides.
Click to expand...

Actually these input registers are just buffers for users data. Actually here is the worst part: I will write the code and the then this code will be placed in Labview environment. What that thing will do with my code, I cant control. At the most I can control things on microscopic level, and that's what I am after. Like controlling things with the help of either library functions or through core generated cores.
 

65 x 8-bit registers should not use 15% of a Zynq logic, even of smaller ones. There is something more wasting your logic.

You can make a single register array (I suggest a 64x8 bits) in a new dummy project and check how much logic this register array uses.
 

tahirsengine said:
Actually these input registers are just buffers for users data. Actually here is the worst part: I will write the code and the then this code will be placed in Labview environment. What that thing will do with my code, I cant control. At the most I can control things on microscopic level, and that's what I am after. Like controlling things with the help of either library functions or through core generated cores.
Click to expand...
Huh? Is this code going into an FPGA or lab view. Those are two totally different things?
 

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