AbinayaSivam
Member level 1
Hello,
I am running 32-bit counter in Quartus. I have used the PIO to read the data but i am facing the problem, data is not in sequence in which PIO receiving the data slowly from FPGA. So, i think FIFO is best to store and read the data in NIOS.
I am new to the altera, please anyone share the FIFO example design or else guide me in FIFO design.
I have attached the Screenshot of the design in which i have used PIO.
https://forums.intel.com/s/question/0D50P000041tK2g/how-to-print-counter-output-in-nios-console-?s1oid=00DU0000000YT3c&OpenCommentForEdit=1&s1nid=0DB0P000000U1Hq&emkind=chatterCommentNotification&s1uid=0050P000008Ifj2&emtm=1536152201613&fromEmail=1&s1ext=0
I am running 32-bit counter in Quartus. I have used the PIO to read the data but i am facing the problem, data is not in sequence in which PIO receiving the data slowly from FPGA. So, i think FIFO is best to store and read the data in NIOS.
I am new to the altera, please anyone share the FIFO example design or else guide me in FIFO design.
I have attached the Screenshot of the design in which i have used PIO.
https://forums.intel.com/s/question/0D50P000041tK2g/how-to-print-counter-output-in-nios-console-?s1oid=00DU0000000YT3c&OpenCommentForEdit=1&s1nid=0DB0P000000U1Hq&emkind=chatterCommentNotification&s1uid=0050P000008Ifj2&emtm=1536152201613&fromEmail=1&s1ext=0