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Separating grounds in analog IC

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MaryF

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Hello,

Is there any way to separate grounds in an analog IC.
I made gnd_x ( ; x = the block number) pin for each block in the circuit but since these grounds are connected to the guard rings of nmos s and that nmoses are built directly in the substrate, I get shorts involving these ground nets in the LVS !
In the cmos p-process that I am using, I don't have a p-well layer to isolate these nmoses! How could I solve this issue?

Thanks,
 

Substrate isolation is done by using triple well layer (usually named deep-n-well), a deep n-well layer allows you to create isolated pwell between nwells. But If the cmos process you are using does not have triple well support then you cannot isolate pwell's therefore you cannot have separate substrate connection.
 

Do you want to separate these ground nets in LVS only or in real life?

In LVS, I think you can achieve that using sconnect (soft connect) in Calibre rule deck for connectivity statements for the substrate / well layers.
But you need to know what you are doing, otherwise you can run into problems.
 

Actually, I need them to be separated in real life !
 

Of course there are ways, varying in how well, how far and
the cost of so doing, .

Figuring out the right or best practical way, is the challenge
and figuring that out may need you to go deeper than just
circuit design to performance goals. Knowing what currents
want to go where, who's sensitive and who's not, to what?
That's some mixture of art, imagination, experience and
detective work. Experience being accrued mostly from
failures, which may not be accounted for in the plan.
 

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