AbinayaSivam
Member level 1
I am getting an error while compiling the code in Quartus software tool. Please suggest me .
Top Module
Code:
module counter
#(parameter WIDTH=8)
(
input clk, enable, rst_n,
output reg [WIDTH-1:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule
Top Module
Code:
module Counter_Top_Level_design
(
input clk,
input rst_n,
output [7:0] out
);
wire counter_enable;
counter counter_inst (
.clk ( clk ),
.rst_n ( rst_n ),
.enable ( counter_enable ),
.count ( out )
);
// For simulation, use this instantiation:
/*niosii_system_tb_niosii_system_inst niosii_system_inst (
.clk_clk ( clk ), // clk.clk
.reset_reset_n ( rst_n ), // reset.reset_n
.output_pio_export ( counter_enable ) // output_pio.export
);*/
// For synthesis, use this instantiation:
NIOS_SYSTEM niosii_system_inst (
.clk_clk ( clk ), // clk.clk
.reset_reset_n ( rst_n ), // reset.reset_n
.output_pio_export ( counter_enable ), // output_pio.export
.counter_out_export (out)
);
endmodule