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Verilog : synthesis Error

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AbinayaSivam

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I am getting an error while compiling the code in Quartus software tool. Please suggest me .

Code:
module counter
#(parameter WIDTH=8)
(
	input clk, enable, rst_n,
	output reg [WIDTH-1:0] count
);

	always @ (posedge clk or negedge rst_n)
	begin
		if (~rst_n)
			count <= 0;
		else if (enable == 1'b1)
			count <= count + 1;
	end

endmodule

Top Module
Code:
module Counter_Top_Level_design
(
	input				clk,
	input				rst_n,
	output [7:0] out
);

wire counter_enable;

counter counter_inst (
		.clk			( clk ),
		.rst_n		( rst_n ),
		.enable		( counter_enable ),
		.count		( out )
	);
	

// For simulation, use this instantiation:
/*niosii_system_tb_niosii_system_inst niosii_system_inst (
		.clk_clk           ( clk ),					//        clk.clk
		.reset_reset_n     ( rst_n ),					//      reset.reset_n
		.output_pio_export ( counter_enable )		// output_pio.export
	);*/
	
// For synthesis, use this instantiation:

NIOS_SYSTEM niosii_system_inst (
		.clk_clk           ( clk ),					//        clk.clk
		.reset_reset_n     ( rst_n ),					//      reset.reset_n
		.output_pio_export ( counter_enable ),	// output_pio.export
		.counter_out_export (out)
	);

endmodule
 

Attachments

  • Ver_error.JPG
    Ver_error.JPG
    84.7 KB · Views: 134

You have connected out to the .count port of your counter and the counter_out_export from the nios_system
 

You have connected out to the .count port of your counter and the counter_out_export from the nios_system


So, what is wrong ? Please point out the error and tell me the solution
 

Chose which one you want the out connected to. You cannot connect a wire to two drivers. Think of what would happen if you tried that on a circuit board.
 

Chose which one you want the out connected to. You cannot connect a wire to two drivers. Think of what would happen if you tried that on a circuit board.

Please suggest me how to sort it out. I am not expert in HDL, and i am unable to debug the code.

I need to pass the count value from [counter_inst] to counter_out_export [NIOS_SYSTEM niosii_system_inst].
 

make sure counter_out_export is an input to the NIOS System, not an output.
 

You have assigned out to outputs of two module's outputs, that is why you are getting error. assign it to single module and it will work.
 

Hello,

Still i am not unable to sort my issue.

I have simplified the Verilog code. But even its trowing error.

counter_pio_external_connection_export set as PIO: 8-bit output in Qsys. Please debug the codes, it will be grateful

Code:
[ATTACH=CONFIG]148856._xfImport[/ATTACH]

 module Counter_Top_Level_design   
 (
  input clk,
  output reg[7:0] out
  
 );
 
always @(posedge clk) 
begin

 out <= out + 1;
end

NIOS_SYSTEM niosii_system_inst (
		.clk_clk           (clk ),					//        clk.clk
		.counter_pio_external_connection_export (out)
	);

endmodule
 

This is the same problem as before. You need to work out which two signals are driving against either other - it tells you in the errors.
 

You have assigned out once here
"always @(posedge clk)
begin

out <= out + 1;
end"

and second time here

"
NIOS_SYSTEM niosii_system_inst (
.clk_clk (clk ), // clk.clk
.counter_pio_external_connection_export (out)"





use it once
 

Hope the following code is right. I have attached the design flow
Code:
module counter

(
	input clk, enable, rst_n,
	output  reg[7:0] count
);

	always @ (posedge clk or negedge rst_n)
	begin
		if (~rst_n)
			count <= 0;
		else if (enable == 1'b1)
			count <= count + 1;
	end
endmodule

Code:
 module Counter_Top_Level_design   
 (
	input				clk,
	input				rst_n,
	output [7:0]	out
	
);

wire counter_enable;
counter counter_inst (
		.clk			( clk ),
		.rst_n		( rst_n ),
		.enable		( counter_enable ),
		.count		( out )
	);
NIOS_SYSTEM niosii_system_inst (
		.clk_clk           ( clk ),					//        clk.clk
		.reset_reset_n     ( rst_n ),					//      reset.reset_n
		.enable_external_connection_export ( counter_enable ),		// output_pio.export
		.cout_export ( count )    //PIO [cout_export]- configured as an input -8bit
	);

endmodule
 

Attachments

  • out.JPG
    out.JPG
    36.5 KB · Views: 114

Hope the following code is right.

The compiler is your best friend.

1. Compile the code & test-bench.
2. Run simulation.
3. Observe the results.
 

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