+ Post New Thread
Results 1 to 12 of 12
  1. #1
    Junior Member level 3
    Points: 355, Level: 4

    Join Date
    Jul 2017
    Posts
    30
    Helped
    0 / 0
    Points
    355
    Level
    4

    Verilog : synthesis Error

    I am getting an error while compiling the code in Quartus software tool. Please suggest me .

    Code:
    module counter
    #(parameter WIDTH=8)
    (
    	input clk, enable, rst_n,
    	output reg [WIDTH-1:0] count
    );
    
    	always @ (posedge clk or negedge rst_n)
    	begin
    		if (~rst_n)
    			count <= 0;
    		else if (enable == 1'b1)
    			count <= count + 1;
    	end
    
    endmodule
    Top Module
    Code:
    module Counter_Top_Level_design
    (
    	input				clk,
    	input				rst_n,
    	output [7:0] out
    );
    
    wire counter_enable;
    
    counter counter_inst (
    		.clk			( clk ),
    		.rst_n		( rst_n ),
    		.enable		( counter_enable ),
    		.count		( out )
    	);
    	
    
    // For simulation, use this instantiation:
    /*niosii_system_tb_niosii_system_inst niosii_system_inst (
    		.clk_clk           ( clk ),					//        clk.clk
    		.reset_reset_n     ( rst_n ),					//      reset.reset_n
    		.output_pio_export ( counter_enable )		// output_pio.export
    	);*/
    	
    // For synthesis, use this instantiation:
    
    NIOS_SYSTEM niosii_system_inst (
    		.clk_clk           ( clk ),					//        clk.clk
    		.reset_reset_n     ( rst_n ),					//      reset.reset_n
    		.output_pio_export ( counter_enable ),	// output_pio.export
    		.counter_out_export (out)
    	);
    
    endmodule

  2. #2
    Advanced Member level 5
    Points: 36,622, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,690
    Helped
    1950 / 1950
    Points
    36,622
    Level
    46

    Re: Verilog : synthesis Error

    You have connected out to the .count port of your counter and the counter_out_export from the nios_system



    •   AltAdvertisment

        
       

  3. #3
    Junior Member level 3
    Points: 355, Level: 4

    Join Date
    Jul 2017
    Posts
    30
    Helped
    0 / 0
    Points
    355
    Level
    4

    Re: Verilog : synthesis Error

    Quote Originally Posted by TrickyDicky View Post
    You have connected out to the .count port of your counter and the counter_out_export from the nios_system

    So, what is wrong ? Please point out the error and tell me the solution



    •   AltAdvertisment

        
       

  4. #4
    Advanced Member level 5
    Points: 36,622, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,690
    Helped
    1950 / 1950
    Points
    36,622
    Level
    46

    Re: Verilog : synthesis Error

    Chose which one you want the out connected to. You cannot connect a wire to two drivers. Think of what would happen if you tried that on a circuit board.



  5. #5
    Junior Member level 3
    Points: 355, Level: 4

    Join Date
    Jul 2017
    Posts
    30
    Helped
    0 / 0
    Points
    355
    Level
    4

    Re: Verilog : synthesis Error

    Quote Originally Posted by TrickyDicky View Post
    Chose which one you want the out connected to. You cannot connect a wire to two drivers. Think of what would happen if you tried that on a circuit board.
    Please suggest me how to sort it out. I am not expert in HDL, and i am unable to debug the code.

    I need to pass the count value from [counter_inst] to counter_out_export [NIOS_SYSTEM niosii_system_inst].



    •   AltAdvertisment

        
       

  6. #6
    Advanced Member level 5
    Points: 36,622, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,690
    Helped
    1950 / 1950
    Points
    36,622
    Level
    46

    Re: Verilog : synthesis Error

    make sure counter_out_export is an input to the NIOS System, not an output.



  7. #7
    Full Member level 4
    Points: 2,601, Level: 11
    Achievements:
    7 years registered

    Join Date
    Nov 2009
    Location
    Pakistan
    Posts
    190
    Helped
    19 / 19
    Points
    2,601
    Level
    11

    Re: Verilog : synthesis Error

    You have assigned out to outputs of two module's outputs, that is why you are getting error. assign it to single module and it will work.



  8. #8
    Junior Member level 3
    Points: 355, Level: 4

    Join Date
    Jul 2017
    Posts
    30
    Helped
    0 / 0
    Points
    355
    Level
    4

    Re: Verilog : synthesis Error

    Hello,

    Still i am not unable to sort my issue.

    I have simplified the Verilog code. But even its trowing error.

    counter_pio_external_connection_export set as PIO: 8-bit output in Qsys. Please debug the codes, it will be grateful

    Code:
    Click image for larger version. 
    
    Name:	Ver_error.JPG 
    Views:	4 
    Size:	185.3 KB 
    ID:	148856
    
     module Counter_Top_Level_design   
     (
      input clk,
      output reg[7:0] out
      
     );
     
    always @(posedge clk) 
    begin
    
     out <= out + 1;
    end
    
    NIOS_SYSTEM niosii_system_inst (
    		.clk_clk           (clk ),					//        clk.clk
    		.counter_pio_external_connection_export (out)
    	);
    
    endmodule



    •   AltAdvertisment

        
       

  9. #9
    Advanced Member level 5
    Points: 36,622, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,690
    Helped
    1950 / 1950
    Points
    36,622
    Level
    46

    Re: Verilog : synthesis Error

    This is the same problem as before. You need to work out which two signals are driving against either other - it tells you in the errors.



  10. #10
    Full Member level 4
    Points: 2,601, Level: 11
    Achievements:
    7 years registered

    Join Date
    Nov 2009
    Location
    Pakistan
    Posts
    190
    Helped
    19 / 19
    Points
    2,601
    Level
    11

    Re: Verilog : synthesis Error

    You have assigned out once here
    "always @(posedge clk)
    begin

    out <= out + 1;
    end"

    and second time here

    "
    NIOS_SYSTEM niosii_system_inst (
    .clk_clk (clk ), // clk.clk
    .counter_pio_external_connection_export (out)"





    use it once



  11. #11
    Junior Member level 3
    Points: 355, Level: 4

    Join Date
    Jul 2017
    Posts
    30
    Helped
    0 / 0
    Points
    355
    Level
    4

    Re: Verilog : synthesis Error

    Hope the following code is right. I have attached the design flow
    Code:
    module counter
    
    (
    	input clk, enable, rst_n,
    	output  reg[7:0] count
    );
    
    	always @ (posedge clk or negedge rst_n)
    	begin
    		if (~rst_n)
    			count <= 0;
    		else if (enable == 1'b1)
    			count <= count + 1;
    	end
    endmodule
    Code:
     module Counter_Top_Level_design   
     (
    	input				clk,
    	input				rst_n,
    	output [7:0]	out
    	
    );
    
    wire counter_enable;
    counter counter_inst (
    		.clk			( clk ),
    		.rst_n		( rst_n ),
    		.enable		( counter_enable ),
    		.count		( out )
    	);
    NIOS_SYSTEM niosii_system_inst (
    		.clk_clk           ( clk ),					//        clk.clk
    		.reset_reset_n     ( rst_n ),					//      reset.reset_n
    		.enable_external_connection_export ( counter_enable ),		// output_pio.export
    		.cout_export ( count )    //PIO [cout_export]- configured as an input -8bit
    	);
    
    endmodule



  12. #12
    Advanced Member level 4
    Points: 7,641, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,129
    Helped
    248 / 248
    Points
    7,641
    Level
    20
    Blog Entries
    1

    Re: Verilog : synthesis Error

    Hope the following code is right.
    The compiler is your best friend.

    1. Compile the code & test-bench.
    2. Run simulation.
    3. Observe the results.
    .....yes, I do this for fun!



--[[ ]]--