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4 bit register having parallel flip flops using VHDL

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asad_khan5130

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Hello Everyone
I am learning VHDL. i want to design a register with four parallel flip flops with common clock. can anyone help me in this regard?
 

Thanks KlausSt. but I want to make it using four instances of D flip flops.
i have written this code. can you please verify it.


Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
 
entity reg4 is
   port (d   : in std_logic;
      clear  : in std_logic;
      clk    : in std_logic;
      Qout     : out std_logic);
end reg4;
 
architecture behave of reg4 is
signal Q0,Q1,Q2 : std_logic ;
      
component DFF is
port(D,Clock:in std_logic; Q:inout std_logic);
end component DFF;
begin
FF0: DFF portmap(D=> 1,Clock =>clk, Q=>Q0);
FF1: DFF portmap(D=> Q0,Clock =>clk, Q=>Q1);
FF2: DFF portmap(D=> Q1,Clock =>clk, Q=>Q2);
FF3: DFF portmap(D=> Q2,Clock =>clk, Q=>Qout);
end behave;

 
Last edited by a moderator:

Hi,

As this is a very basic problem...

I recomend you to go through some basic VHDL tutorials.
There are internat pages, PDFs as well as videos.

Klaus

- - - Updated - - -

although ´m not familair with VHDL...
I came across an online tutorial and within a couple of minutes I modified the example to the following code.


Code VHDL - [expand]
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ENTITY register4 IS PORT(
    d   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    clk : IN STD_LOGIC; -- clock.
    q   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- output
);
END register4;
 
ARCHITECTURE description OF register4 IS
 
BEGIN
    process(clk)
    begin
        if rising_edge(clk) then
            q <= d;
        end if;
    end process;
END description;



It shouldn´t be far away for a 4 bit register. Maybe someone can check this.

Klaus

- - - Updated - - -

Hi, (sorry for the wrong order of posts)

As said I´m not familiar with VHDL, but your solution rather looks like a 4 bit serial shift register....with "1" as input instead of "d". It looks weird to me.

Klaus
 

Thanks Klaus. but i want to make it using instances of four flip flops
i have written this code. someone please verify it


Code VHDL - [expand]
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entity reg4 is
port(D,clk : in bit;
       Q: out bit);
end reg4;
 
architecture behave of reg4 is
component DFF 
port(D,clk :inbit; Q:outbit);
end component;
 
signal Q: in bit_vector(2 downto 0);
begin
DFF0: DFF portmap(D =>1, clock =clk, Q=>Q0);
DFF1: DFF portmap(D =>Q0, clock =clk, Q=>Q1);
DFF2: DFF portmap(D =>Q1, clock =clk, Q=>Q2);
DFF3: DFF portmap(D =>Q2, clock =clk, Q=>Q);
end behave;

 
Last edited by a moderator:

This is just a 4 bit shift register that shifts in '1'. It can never be reset. What are you trying to achieve.?
It also has syntax errors.
You should try to compile the code first, and fix the syntax errors.
 

i could not find code on internet. can you please provide me code for 4 bit parallel register using instances of four flip flops.?
 

i could not find code on internet. can you please provide me code for 4 bit parallel register using instances of four flip flops.?

go do your homework. what you need can be described in less than 10 lines of code.
 

any error in this code?
Code:
entity reg4 is
port(d0,d1,d2,d3, clr,clk : in bit;
       q0,q1,q2,q3 : out bit);
end reg4;

architecture structure of reg4 is
component DFF 
port(D,clk :inbit; Q:outbit);
end component;
begin
DFF0: DFF portmap(d0, clock, q0);
DFF1: DFF portmap(d1, clock, q1);
DFF2: DFF portmap(d2, clock, q2);
DFF3: DFF portmap(d3, clock, q3);
end behave;
 
Last edited by a moderator:

Why not run it through a compiler and find out?
 

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