matrixofdynamism
Advanced Member level 2
I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want i.e hardware implement the algorithm. Is this true?
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If you are talking about small algos or IPs to be implemented using HLS yes it is good. But in my opinion designing an entire processor with makes little sense.In VHDL e.g our code directly infers registers, logic gates to implement specific functions like AND, OR e.t.c, it infers memory blocks and DSP blocks, it infers muxes among other things. I wonder how they managed to synthesize hardware from high level description, seems so much more complicated.
But in my opinion designing an entire processor with makes little sense.
Moreover a processor design must be cycle accurate.
I.E the tool infers a RISC CPU microcode to solve the coded HLS problem.I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want
I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want i.e hardware implement the algorithm. Is this true?