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What principles do High Level Synthesis languages use to synthesize hardware?

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matrixofdynamism

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I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want i.e hardware implement the algorithm. Is this true?
 

Sounds strange - I think your're taking it out of context.
Perhaps as a tool for software emulation, functional hardware simulation or some kind of modeling. But as the actual synthesis Netlist product for the ASIC/FPGA? Why?

A "RISC processor" is a sequential being in nature. This kind of misses out the advantages of implementing custom hardware in the first place - that can be minimalistic and parallel (if required).
 

In VHDL e.g our code directly infers registers, logic gates to implement specific functions like AND, OR e.t.c, it infers memory blocks and DSP blocks, it infers muxes among other things. I wonder how they managed to synthesize hardware from high level description, seems so much more complicated.
 

I have some minimal experience with Vivado HLS and while it seems remotely possible that it might infer such a thing sometimes that's not at all how I understand it works generally.

For example I wrote a signal processing pipeline and I'm sure it inferred a straightforward signal processing pipeline much as I would have created in Verilog.
 

I don't think anyone would want to re-invent the wheel with HLS coding, specially when the h/w RISC design is working great on silicon.

In VHDL e.g our code directly infers registers, logic gates to implement specific functions like AND, OR e.t.c, it infers memory blocks and DSP blocks, it infers muxes among other things. I wonder how they managed to synthesize hardware from high level description, seems so much more complicated.
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If you are talking about small algos or IPs to be implemented using HLS yes it is good. But in my opinion designing an entire processor with makes little sense.

Moreover a processor design must be cycle accurate. With HLS coding cycle accurate designs are still not possible. Maybe after 5 years........
 

But in my opinion designing an entire processor with makes little sense.
Moreover a processor design must be cycle accurate.
Click to expand...

As far as I understand - The OP's goal isn't to implement a RISC processor.

I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want
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I.E the tool infers a RISC CPU microcode to solve the coded HLS problem.
Which to me seems sub-optimal to say the least.
 

Are you thinking about something like open CL, where the architecture is a host farming jobs it to custom peripherals that are inferred from the code?
 

matrixofdynamism said:
I have read somewhere that High Level Synthesis languages will infer a RISC processor and microcode it to achieve what we want i.e hardware implement the algorithm. Is this true?
Click to expand...

Hi,

I think you were reading about ASIP (with a 'P') technology, where you generate a processor, that is tuned to your algorithm, written in C. A long time ago, I used Target and OptimoDE (now ARM I think). ASIP - application specific integrated processor.

It effectively generates everything needed (processor but also ISS and compiler toolchain). That is close to high-level synthesis, but not exactly the same : in HLS, the solution generated is not reprogrammable.

Hope this helps
JCLL
 

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