tahirsengine
Member level 3
Hi,
I wanted to create this thread to gather information about the syntax of VHDL that yields the smallest circuitry in synthesis.
Now, as we know that the best way to write codes that yields the smallest circuitry in Synthesis is through library functions. The worst part of these codes comes when you want to port the same code on different FPGA(i.e from Xilinx to Altera).
That mean such codes should be generic so that these can easily be ported towards other platforms.
If you know some of such techniques in VHDL, that produces least circuitry after synthesis then it will be of great value(across different platforms) i.e As I know that if else statement produces more circuitry than ternary operator in Verilog. Similarly, default value in Case structure invokes memory elements, and thus produces more circuitry. But these examples are from Verilog. Want to know such techniques in VHDL.
Please share your knowledge, any link or document on this topic.
Regards
Tahir
I wanted to create this thread to gather information about the syntax of VHDL that yields the smallest circuitry in synthesis.
Now, as we know that the best way to write codes that yields the smallest circuitry in Synthesis is through library functions. The worst part of these codes comes when you want to port the same code on different FPGA(i.e from Xilinx to Altera).
That mean such codes should be generic so that these can easily be ported towards other platforms.
If you know some of such techniques in VHDL, that produces least circuitry after synthesis then it will be of great value(across different platforms) i.e As I know that if else statement produces more circuitry than ternary operator in Verilog. Similarly, default value in Case structure invokes memory elements, and thus produces more circuitry. But these examples are from Verilog. Want to know such techniques in VHDL.
Please share your knowledge, any link or document on this topic.
Regards
Tahir