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Warning in Vivado Design Suite during synthesis

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Radhikamkr

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I was doing synthesis of a verilog code that I had written.

While synthesizing it is throwing a warning :"Parallel synthesis criteria is not met",
Why is this coming?
Please help.
 

Do you have a pragma parallel_case that is not a parallel_case?
 

I haven't added any pragma in the code
 

I think it's only a warning that only one core in your PC can be used for the operation.
 

std_match said:
I think it's only a warning that only one core in your PC can be used for the operation.
Click to expand...

Without context, this might be the right answer. Parallel synthesis is slower than single-thread synthesis for small designs, hence it is avoided.
 
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