How do I synthesize an inout port using DC?

kos8108 said:

ex)...

module test (

input clk;
input a;
inout b;
output c;
)

...

endmodule

I would like to synthesize using dc,the constraint on input & output should be shown below,

set_input_delay -min 1 [get_ports a] -clock clk
set_input_delay -max 2 [get_ports a] -clock clk

set_output_delay -min 0 [get_ports c] -clock clk
set_output_delay -max 1 [get_ports c] -clock clk

but I don't know what to do about Inout pin b

Can I set up one of two ways just like input or output? like this


set_input_delay -min 1 [get_ports b] -clock clk
set_input_delay -max 2 [get_ports b] -clock clk

or

set_output_delay -min 0 [get_ports b] -clock clk
set_output_delay -max 1 [get_ports b] -clock clk

Please help me.

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