TSMC n65 substrate contact for rf mos/power net layout/Latchup prevention

Hi team,
May I please ask a few questions?

Part 1--deep nwell nmos guardring
I'm using TSMC 65nm pdk to layout an analog circuit. I noticed all the "nmos_rf" are in deep nwell process and "pmos_rf" are regular nwell process.
1. For pmos_rf, I can just connect the guard ring (created by PDK default) to my vdd mesh to create a good latch up prevention
2. For nmos_rf, there are only 2 level of guard rings created by pdk: a) The guardring in the pwell inside of the deep nwell, which connects the pwell to gnd. b) The guardring in the deep nwell, which connects the nwell to vdd.

Q1:My first question is that for latchup prevention, should I manually add another level of guardring to ground the p-sub surround the nwell for latch up consideration? Or is that since the pmos is well grounded, no feedback loop can be formed so there should not be a latchup?

Part 2--the power/ground mesh layout.
Previously, I was literally layout the rows and columns of horizontal/vertical M1/M2 thin traces for gnd/vdd and connect the trace to the guardring of my rf mos and appropriate place in the circuit. Recently, my professor have mentioned another approach:
1. Create a unit filler cell with a unit layout connect M1,3,5,7 to gnd and M2,4,6 to vdd
2. Add substrate contact form M1 to gnd.(He said there is no such thing as too much substrate contact)
3. Fill the opening in your layout with this small unit filler.
My questions is
Q2.In that case, is my local circuit is going to look like a valley surrounded from all 4 directions. I assume the way to connect two local cell is going to create another unit cell and leave one of the layer missing so my signal trace can use such layer to pass through?
Q3.My professor said In the case of add substrate contact in the unit cell, I should not add decoupling cap from vdd to ground in the unit cell. Can anyone explain why the decoupling cap and substrate contact are mutually exclusive?
Q4. To my understand, the purpose of such unit cell substrate contact is to prevent latchup. So if I add the third guardring as the Part1 to prevant latchup, is there any extra benefit for the substrate contact in the filler cells?

Thanks

Q1: No, another (third) guardring to GND around the nwell isn't necessary to prevent latchup. But also see my answer to Q4.

Q2: Right.

Q3: Decoupling caps need a lot of area to create a reasonable amount of capacitance. They shouldn't be integrated in your unit cells for GND or VDD contact, but fill areas which otherwise would be empty.

Q4: As stated in my answer to Q1, you don't need a third guardring to GND around any nwell for latchup prevention.

But there could be another reason for such a third guardring to GND: to screen (attenuate) signals - like clock or other fast switching signals - to penetrate (couple) into or out from the cell(s) in the nwell via the substrate.

Hi erikl
Thanks for your reply.
Q1&Q4 Please correct me if I were wrong. If I only use deep nwell nmos (2 GR for pwell to gnd and nwell to gnd )and regular pmos（ 1 GR for nwell to vdd), without a third guardring, the p-sub are in fact floating But the psub, which everything is build on, is not connect to anything....

Q3 I am thinking of using nmos cap. I understand I need many of them for good enough decoupling capacitance. Are you suggesting a few big caps or parallel many many small caps? Because if I apply the setup from Q2, by adding a small nmos cap to each unit filler cell, and use them to "fill areas which otherwise would be empty." , the model of which would be a net of parallel connected caps. Will that have any drawbacks?

Thank you so much
Allen

AllenD said:

Q1&Q4 Please correct me if I were wrong. If I only use deep nwell nmos (2 GR for pwell to gnd and nwell to gnd )

Click to expand...

No: nwell to vdd

AllenD said:

... the p-sub are in fact floating But the psub, which everything is build on, is not connect to anything....

Click to expand...

Of course psub must'nt be kept floating: Somewhere it must be connected via a large area p+ implant, contacts, M1, vias up to top metal and then to a real GND pad. And your prof. is quite right saying "there is no such thing as too many substrate contacts". So a third p+ on psub guardring - connected via contacts to M1 and then to GND metal - is quite welcome if you have enough space.

But it is not necessary for additional protection against latchup.

AllenD said:

Q3 I am thinking of using nmos cap. I understand I need many of them for good enough decoupling capacitance. Are you suggesting a few big caps or parallel many many small caps? Because if I apply the setup from Q2, by adding a small nmos cap to each unit filler cell, and use them to "fill areas which otherwise would be empty." , the model of which would be a net of parallel connected caps. Will that have any drawbacks?

Click to expand...

I understand your unit filler cells are primarily meant for good GND resp. VDD contact - and for this purpose wouldn't need much area. Sensible decoupling caps - to actually satisfy their purpose of decoupling - should have a capacitance of at least ten times the total capacitance of the "working" transistors whose power supply they are meant to decouple - which would be at least in the order of 100fF, perhaps 1pF or more. Hence decoupling caps of - at least - 1pF would be meaningful. In your technology - with tox≈3nm and Cox ≈ 11.5 fF/µm² , a single 1pF cap will need an area of 87µm² or about 10µm x 10µm - which probably is much larger than the area used for the active FETs you want to decouple. That's why power supply decoupling caps usually won't be integrated into PMOS or NMOS or even full cell sectors, but much more after placing all the circuit's cells - and then filling the (otherwise) empty areas between them with a lot of small decaps - a single one not larger than 10µm x 10µm.

Hi erikl
Much obliged for your response. That's very educational.

erikl said:

I understand your unit filler cells are primarily meant for good GND resp. VDD contact - and for this purpose wouldn't need many areas.

Click to expand...

Yes, that's exactly my primary purpose of unit filler cell. As is depicted in the picture(left is one of my local circuit view and right is the zoom in. Small squares are my filler cells and big squares are my mosfets) I use the filler cell to both surround my local circuit view and fill in the opening area inside the local circuit view to create a better GND/VDD connection to each of the MOS transistor. Do you think I overkill the problem(maybe I put too many unit filler cells than necessary? maybe too much parasitic caps will be generated?) I am a bit worried about your comments "wouldn't need many areas". The size of my unit filler cell is 2.5µm x 2.5µm with M1,3,5,7 and psub contact connected together and M2,4,6 connected together. Do you think the unit filler cell is too big?

erikl said:

Sensible decoupling caps - to actually satisfy their purpose of decoupling - should have a capacitance of at least ten times the total capacitance of the "working" transistors whose power supply they are meant to decouple - which would be at least in the order of 100fF, perhaps 1pF or more. Hence decoupling caps of - at least - 1pF would be meaningful. In your technology - with tox≈3nm and Cox ≈ 11.5 fF/µm² , a single 1pF cap will need an area of 87µm² or about 10µm x 10µm - which probably is much larger than the area used for the active FETs you want to decouple. That's why power supply decoupling caps usually won't be integrated into PMOS or NMOS or even full cell sectors, but much more after placing all the circuit's cells - and then filling the (otherwise) empty areas between them with a lot of small decaps - a single one not larger than 10µm x 10µm.

Click to expand...

There is one more thing that got me confused. In your example, if we assumed "the total capacitance of the "working" transistors whose power supply they are meant to decouple" is 1000fF. Then I would need 10 of 10µm x 10µm decoupling cap, which I should build in the global view instead of the local view. So intuitively speaking, If I have 2 identical local cells like you described, I would put at least 20 of 10µm x 10µm cap (or other combination of the same capacitance) for a good decoupling.

But why should I use “a lot of small decaps - a single one not larger than 10µm x 10µm.” Is the reason that a lot of small decaps is better than a large decap is that the placement of the decap is more flexible? Is the bigger the total decap capacitance, the better? if so, why do you limit each one of the decap should not bigger than 10µm x 10µm?

Thank you so much and I genuinely appreciate your help
Allen

AllenD said:

As is depicted in the picture(left is one of my local circuit view and right is the zoom in. Small squares are my filler cells and big squares are my mosfets) I use the filler cell to both surround my local circuit view and fill in the opening area inside the local circuit view to create a better GND/VDD connection to each of the MOS transistor. Do you think I overkill the problem(maybe I put too many unit filler cells than necessary?

Click to expand...

No, your layout is just fine in regard to "filling in the open area inside the local circuit" - for creating a better GND/VDD connection to each of the MOS transistors it's a bit too much. Keep your layout as it is, it looks very good and symmetrical for an educational design, which you don't have to pay its footprint area for. For a high volume design, however, - produced in millions of chips - you'd have to be more penny-pinching with area usage.

AllenD said:

maybe too much parasitic caps will be generated?)

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Not at all: parasitic caps of your filler cells don't count as parasitic - in contrary: actually they represent mini decaps, because they are either at GND potential (so their cap just enlarges the GND capacity) or between VDD & GND.

AllenD said:

I am a bit worried about your comments "wouldn't need many areas". The size of my unit filler cell is 2.5µm x 2.5µm with M1,3,5,7 and psub contact connected together and M2,4,6 connected together. Do you think the unit filler cell is too big?

View attachment 148691

Click to expand...

For a decision, just review my above comment about educational in contrast to a high volume design.

AllenD said:

There is one more thing that got me confused. In your example, if we assumed "the total capacitance of the "working" transistors whose power supply they are meant to decouple" is 1000fF. Then I would need 10 of 10µm x 10µm decoupling cap, which I should build in the global view instead of the local view. So intuitively speaking, If I have 2 identical local cells like you described, I would put at least 20 of 10µm x 10µm cap (or other combination of the same capacitance) for a good decoupling.

Click to expand...

Right. But you'd place them into otherwise empty areas, which usually cannot be avoided after final cell placement.

Also, in regard to the necessary amount of decoupling, the type of circuit has to be considered: high frequency fast switching cells may need (a lot) more decoupling than low frequency / low power circuit cells.

AllenD said:

But why should I use “a lot of small decaps - a single one not larger than 10µm x 10µm.” Is the reason that a lot of small decaps is better than a large decap is that the placement of the decap is more flexible? Is the bigger the total decap capacitance, the better?

Click to expand...

Both reasons are true. Regarding the latter, you need a compromise: decaps cost area, area=money. As many decaps as necessary, but no more. That's why one usually fills just the otherwise unused areas with decaps: no additional costs.

AllenD said:

if so, why do you limit each one of the decap should not bigger than 10µm x 10µm?

Click to expand...

Decaps need connections, and connections add parasitic resistivity. For low-resistance connectivity one should use many contacts to M1, and connections as short as possible. This is easier realizable with not too big decaps.

Hi erikl
You are a life saver!!
Can I ask you one more question,please? You have confirmed that "my local circuit is going to look like a valley surrounded from all 4 directions. I assume the way to connect two local cell is going to create another unit cell and leave one of the layer missing so my signal trace can use such layer to pass through".

I am a little concerned about the parasitic capacitance created by such "hole on the wall". Here I have several ways to mitigate such issue.
1. Since the unit filler cell are just from M1-M7 and M8-M9 are thick metal layers. I can via up the input/output of each local cell and connect them on M8 or M9
2. I can "dig a bigger hole on the wall" by not just leaving one layer open. Instead, I would leave 3 layers open. (for example, if I want to use M5 to connect 2 local cells, I will create a filler cell and leave M4-M6 open)
3. I can taper off the signal trace. In other words, I can make the width of the section of the trace, which go through the "hole", thinner and expand the trace to its previous thickness after the hole.

Which way do you think is the best? please don't hesitate to share your insight if you have a better solution or don't think this parasitic capacitance is a problem. (My signal frequency is 300MHz with 3 GHz sample rate)

Thanks
Allen

I think your no. 1 or 2 suggestions (routing the signal connection up and down again) would create too much and unnecessary parasitic. Take the shortest route, as possible.

Your no. 3 suggestion is the best, I guess. Stay at M1 with your signal connection(s), and create/integrate one or more free M1 path(s) through your filler cells. Keep enough distance between the signal path(s) and GND/VDD M1 and perhaps M2, too, to keep signal parasitics low.

Tapering metal traces (re. width) will not be allowed by your technology DRC rules, I suppose. Always use minimum width for signal paths, they normally don't have to deliver power in CMOS (don't have to provide much current load).

Hi erikl
Thanks for you confirmation and valuable suggestions!

erikl said:

Your no. 3 suggestion is the best, I guess. Stay at M1 with your signal connection(s), and create/integrate one or more free M1 path(s) through your filler cells. Keep enough distance between the signal path(s) and GND/VDD M1 and perhaps M2, too, to keep signal parasitics low.

Click to expand...

Can I please ask why do you suggest I should use M1 for all the signal connection between cells? If the output of the local circuit just happen to be on , for example,M4. Should I just use M4 as the layer to connect different local cells(and leave M3,M4 and M5 open for reduced coupling)? Besides, I am under the impression that M1 is not only very thin(high parasitic resistance) and its coupling to substrate is the worst compare to the higher layers.

erikl said:

Always use minimum width for signal paths, they normally don't have to deliver power in CMOS (don't have to provide much current load).

Click to expand...

Is this because normally the receiving end of the signal path is a mosfet gate with infinite resistance? Assuming I need to connect the output of the local cell A to the input of the local cell B. If the input of the local cell B is a diode connected nmos(small input impedance=~1/gm), then I probably have to consider to use a wider trace?

Thanks
Allen

AllenD said:

Can I please ask why do you suggest I should use M1 for all the signal connection between cells? If the output of the local circuit just happen to be on , for example,M4. Should I just use M4 as the layer to connect different local cells(and leave M3,M4 and M5 open for reduced coupling)?

Click to expand...

Sure, use M4 in this case. Just remove M3, M4 & M5 GND/VDD far enough away from the M4 signal connection to keep its parasitic low.

AllenD said:

Besides, I am under the impression that M1 is not only very thin (high parasitic resistance) and its coupling to substrate is the worst compare to the higher layers.

Click to expand...

You are right. I just thought your signal I/O connections would be on M1. Always try and use the shortest signal connection.

AllenD said:

Is this because normally the receiving end of the signal path is a mosfet gate with infinite resistance? Assuming I need to connect the output of the local cell A to the input of the local cell B. If the input of the local cell B is a diode connected nmos(small input impedance=~1/gm), then I probably have to consider to use a wider trace?

Click to expand...

Yes, but also consider the short connection length! Calculate/estimate the series resistance, then decide on the necessary width. Be aware that the additional parasitic capacitance of wider signal connection often nullifies the conductivity gain by the wider path, at least at high frequencies - not for a DC current source connection (if so), of course.

Thank you for your help all alone! Much appreciated!

erikl said:

Always use minimum width for signal paths, they normally don't have to deliver power in CMOS (don't have to provide much current load).

Click to expand...

This is a questionable recommendation.
If you worry about the delay, and when delay is limited by the signal net resistance (and net or load capacitance), and hence you want to minimize the net resistance - you should not be using minimal width metal.
In advanced nodes, interconnects (both metals and vias) are highly resistive, and often cause RC delay violations.