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[SOLVED] FSM model in verilog

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jasmine123

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I have tried to replace the while with a FSM model. But not successful in doing so. The output which is k is not passed to the output port.

Code: 
1:      while T[16] = 1 do // if (MSB bit of T==1)
2:           T[16] = 0 //set the MSB bit to 0
3:            T = T + (2**16 mod Y ) //and a precomputed value and if MSB bit is again 1 then repeat from line 8
       return T

Code: 
module fsm_model(clk,t,r,k);
input clk;
input [16:0] t;
input [16:0] r;
output reg [16:0] k;
reg  state;
reg [16:0] g;
reg [16:0] h;
always @ (posedge clk) 
begin 
		h = t;
		state = h[16];
		case (state)
		1'b0: 
		begin
				k = {1'b0,h[15:0]};
				state = 0;
		end
		1'b1:
		begin
				g = {1'b0,h[15:0]};
				h = g[16:0]+ r[16:0];
				if (h[16:0] > 16'hFFFF)
					state = 1'b1;
				else 
					state = 1'b0;
		end
		endcase
end		
endmodule
 

you state variable can never get into the 1'b1 state. When its 0 , it stays in 0 forever.
Why not show a simulation waveform, and show whatr the error is?
 

fsm_model.jpg

I referred some examples online, where they were able to shift from online to another. https://electrosofts.com/verilog/fsm.html
 

You need to learn FSM design and verilog in general. Start by the difference between blocking and non-blocking assignment. Then learn about FSM templates.
 

I did the changes with regard to the statements and the logic and this is what I have. But I am getting an error which I am unable to solve.

Code Verilog - [expand]
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module fsm_model(clk,t,r,k,rst);
input clk,rst;
input [16:0] t;
input [16:0] r;
output reg [16:0] k;
reg  state;
reg [16:0] g;
reg [16:0] h;
parameter s1 = 1'b0;
parameter s2 = 1'b1;
reg next_state;
always @ (posedge clk or negedge rst) 
begin
        if (rst) 
                state <= s1;
        else 
                state <= next_state;
end
always @(t or state)
begin
        h <= t;
        case (state)
        s1: 
        begin
                if (h[16]) begin 
                    g <= {1'b0,h[15:0]};
                    h <= g[16:0]+ r[16:0];
                    next_state <= s2; end
                else 
                    next_state <= s1;      // line 42
        end
        s2:
        begin
                if (h[16]) begin
                        g <= {1'b0,h[15:0]};
                            h <= g[16:0]+ r[16:0];
                        next_state <= s2; end
                else 
                        next_state <= s1;
                end
        endcase
        k <= h;
        end     
endmodule



Error:

Code: 
HDLCompiler:1128 - "D:\project\new\montegomery\fsm_model.v" Line 42: Assignment under multiple single edges is not supported for synthesis
 
Last edited by a moderator:

jasmine123 said:
I did the changes with regard to the statements and the logic and this is what I have. But I am getting an error which I am unable to solve.

Code Verilog - [expand]
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module fsm_model(clk,t,r,k,rst);
input clk,rst;
input [16:0] t;
input [16:0] r;
output reg [16:0] k;
reg  state;
reg [16:0] g;
reg [16:0] h;
parameter s1 = 1'b0;
parameter s2 = 1'b1;
reg next_state;
always @ (posedge clk or negedge rst) 
begin
        if (rst) 
                state <= s1;
        else 
                state <= next_state;
end
always @(t or state)
begin
        h <= t;
        case (state)
        s1: 
        begin
                if (h[16]) begin 
                    g <= {1'b0,h[15:0]};
                    h <= g[16:0]+ r[16:0];
                    next_state <= s2; end
                else 
                    next_state <= s1;      // line 42
        end
        s2:
        begin
                if (h[16]) begin
                        g <= {1'b0,h[15:0]};
                            h <= g[16:0]+ r[16:0];
                        next_state <= s2; end
                else 
                        next_state <= s1;
                end
        endcase
        k <= h;
        end     
endmodule



Error:

Code: 
HDLCompiler:1128 - "D:\project\new\montegomery\fsm_model.v" Line 42: Assignment under multiple single edges is not supported for synthesis
Click to expand...

Please, for your own sake, learn the difference between blocking and non-blocking assignments and how they are used to model combinational and sequential logic.
 

Despite of other possible problems, the mentioned error is almost trivial and caused by a wrong polarity of rst that doesn't match the template for register synthesis. Presuming rst has active high level, you should write
Code Verilog - [expand]
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always @ (posedge clk or posedge rst) 
begin
        if (rst) 
                state <= s1;
        else 
                state <= next_state;
end


Otherwise write if (!rst). The reported error line 42 is wrong.
 

The Xilinx's recommendation is not to use reset at all in the sensitivity list if it is not necessary like this time.
Use only clk like below to create flip-flop without additional control signals.

Code Verilog - [expand]
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always @ (posedge clk) 
begin
        if (rst) 
                state <= s1;
        else 
                state <= next_state;
end


This error at line 44 is valid because "h" (and indirectly "k" at line 44) could be updated on both - when "t" changed or when "state" changed at the same time.

Please check out FSM templates in ISE/Vivado for Verilog. I prefer to write synchronous one-always block for FSM (for working out next state and outputs all in the next clock cycle).
 

The Xilinx's recommendation is not to use reset at all in the sensitivity list if it is not necessary like this time.
Click to expand...

It's a different hardware description, omitting posedge rst in the event expression generates a synchronous reset while the original code obviously intends an asynchronous reset. Both have their purpose, but I don't believe that Xilinx considers asynchronous resets as unnecessary.
 

The Xilinx's recommendation is not to use reset at all in the sensitivity list if it is not necessary like this time
Click to expand...
.
@ niciki
Only if the reset is synchronous to the clock used in the sensitivity list.
 

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