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  1. #1
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    Auto routing constraints in cadence virtuoso

    I would like to know what type of constraints could be set in the auto router tool in virtuoso ADE GXL. I am working on optimum routing solution for our technology where we are using our own developed PDK. Typically the designs are small but we have some critical constraints.

    For example:

    1) Single metal layer is available for routing. There is another metal layer but its length is limited. It can only be used as a jumper for example. Can I add a length constraint and cost to any metal layer in the ADE GXL? By increasing the cost the router will avoid using it until it doesn't find any other solution. By limiting its length it would only be used as the jumper.

    2) Can I assign some nets as critical nets or critical pins ? By assigning some nets as critical, is it possible that router would avoid placing jumpers on that net ? Can I set such a constraint?

    3) Can I set a routing sequence of nets? By routing sequence I mean how router will route nets one by one based on the input sequence of the nets.

    Our PDK is in the early development stages and not all of the PDK components are functional. Could anyone please tell me which information/functions should be added in the technology file to be able to use auto router ? or if someone could tell me the document that explains how to setup the auto router that would also be helpful.

    I am using Virtuoso 6.1.6

    Thanks

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  2. #2
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    Re: Auto routing constraints in cadence virtuoso

    Hi, I have question, analog layout Could be auto-routed?

    or your problem is only for digital layout?



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  3. #3
    Junior Member level 1
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    Re: Auto routing constraints in cadence virtuoso

    Yes, It can auto-routed but your routing is very much dependent on the placement. So, good placement will lead to good routing. My problem is related to analog layout but I don't have very hard constraints and typically I am working with very small circuits.



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