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[SOLVED] record issue with quartus 15.1

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nsgil85

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Hi

I have this piece of code:

Code: 
entity U1 is 	
	generic
	(
		POS_CONFIG_1							: positive := 8;		
		POS_CONFIG_2							: positive := 75;		
		POS_CONFIG_3							: positive := 10;		
		POS_CONFIG_4							: positive := 48;		
		POS_CONFIG_5							: positive := 4		  
	) ;
	port				    																
	( 	

	
		IN_REC_DVP_BUS : in DvpBus(data(POS_CONFIG_1-1 downto 0),
											xpos(bwidth(POS_CONFIG_2+POS_CONFIG_3)-1 downto 0),
										       ypos(bwidth(POS_CONFIG_4+POS_CONFIG_5)-1 downto 0));
		
		OUT_REC_DVP_BUS : out DvpBus(data(POS_CONFIG_1-1 downto 0),
									 xpos(bwidth(POS_CONFIG_2+POS_CONFIG_3)-1 downto 0),
									 ypos(bwidth(POS_CONFIG_4+POS_CONFIG_5)-1 downto 0));		

		
		CLK_0 		: in std_logic ; 					
		RST_0		: in std_logic 		
	) ;   
end entity U1;

in a package i have the record declaration (unconstrained):
Code: 
type DvpBus is record
   SAMP  		: std_logic;
   VALID		: std_logic;
   DATA 		: std_logic_vector;  
   XPOS	        : unsigned;
   YPOS	        : unsigned;

end record DvpBus;

modelsim is able to compile it, but quartus not (VHDL 2008).
how can i overcome this without constraint the record in the package?

thanks
 

Quartus VHDL 2008 support is far from full - and don't expect it to change.
It supports unconstrained array with no problem but I'm not sure that unconstrained records are unsupported.

Anyway,
You should post the error massage.

- - - Updated - - -

P.S: I've just seen that you use Q15.1.
Try a later version.
 

Code: 
Error (10410): VHDL Type Conversion error at u1.vhd(71): Type Conversion near text or symbol "DvpBus" must have one argument
 

1. Try to constrain the record elements and see if the error goes away.
2. If it does - try again with a newer version of Quartus.
 

1. Try to constrain the record elements and see if the error goes away.
Click to expand...
Tried, it pass compilation.

2. If it does - try again with a newer version of Quartus.
Click to expand...
neither version 18.0 support such an error

any idea how to overcome this?
 

Did you remember to turn on Vhdl 2008 support in Quartus?
 

Did you remember to turn on Vhdl 2008 support in Quartus?
Click to expand...
Yep!, still not accepted.
Does Vivado can handle such an error?
 

I did use Vivado with various VHDL 2008 language constructs successfully.
Regarding this particular usage case - I don't use records that often so I can't say.

Try it...
 
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