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XML file generation from VHDL/Verilog

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tahirsengine

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Hi,
I have some VHDL/Verilog code files, and I need to generate XML based hardware specifications files out of it.
Is there any way I can generated these files through software? I know/have Quartus and Vivado/ISE with me.

Thanks and Cheers

Tahir
 

Cant you use TCL scripts to generate the XML files, that could be generated during the compilation flow?
 

TrickyDicky said:
Cant you use TCL scripts to generate the XML files, that could be generated during the compilation flow?
Click to expand...

Thanks for replying.
I searched all the directory, and can't find the XML file. Although there are some XML file. but surely they are not what I need.
So, can you please inform how to generate hardware specifications XML files with the TCL?
 

FvM said:
Are you referring to a specific specification standard? Please clarify.
Click to expand...

I need to generate XML based hardware specifications file of the modules within my design. (I seriously dont know what this hardware specifications XML means). But yes I know a little bit format of these files. I checked all generated XML files within my project. So surely they are not what I requires.
I know up till this.

Hint: Actually, I want to import these files to Labview CLIP. And Labview CLIP only accepts xml files of the hardware. Now this the main problem.
 

Without knowing what you're trying to output, there is little we can do.
What does this XML contain? XML itself is pretty meaningless without some destination format.
I doubt many people use Labview CLIP here - and there must be tools for creating the appropriate XML.
 

Maybe you are talking about IP-XACT standard?
You can generate Component.xml file in Vivado for your IP by Packaging feature.
You can find all Xilinx's IPs described in IP-XACT standard in the following folder: ...\Vivado\<version>\data\ip\xilinx
 

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