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[SOLVED] while condition in verilog

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jasmine123

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Hi,
I am trying to implement a particular algorithm in verilog whose pseudo code is given below. I have problem with the while loop(LINE 7 & 11). I get this error when the while loop is used; Non-constant loop condition not supported for while. Can someone suggest me an alternative.

Code:
Compute: X mod Y
1: G = Split(X;Width(Y ) )//split x in widths of y
2: N = Num(G) - 1// no. of groups that x is split into
3: while N > 0 do
4: T = G[N]
5: for i = Width(Y ) - 1 downto 0 do
6:      T = T << 1
7:      while T[Width(Y )] = 1 do // if (MSB bit of T==1)
8:           T[Width(Y )] = 0 //set the MSB bit to 0
9:            T = T + (2**Width(Y ) mod Y ) //and a precomputed value and MSB bit is again 1 then repeat from line 8
10: G[N - 1] = G[N - 1] + T
11:while G[N - 1][Width(Y )] = 1 do // if (MSB bit of G[N-1]==1)
12:      G[N - 1]Width(Y ) = 0
13:      G[N - 1] = G[N - 1] + (2**Width(Y ) mod Y )
14: N = N - 1
15: while G[0] > Y do
16: G[0] = G[0] - Y
      return G[0]
 

HDL iteration loops are a means to generate parallel logic. For hardware synthesis, the number of iterations respectively parallel instances must be known at compile time. A possible solution is to determine the maximal iteration count according to input number range and design the loop for this number with an additional termination condition.

Alternatively, a sequential (FSM based) implementation may be preferred.
 
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