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[SOLVED] std_logic conversion

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nsgil85

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Hi

suppose i have this procedure:
Code: 
	procedure registery(signal 	clock 			: in std_logic; 
						signal 	rst 			: in std_logic; 
						signal 	input 			: in std_logic_vector; 
						signal 	output 			: out std_logic_vector)is	

	begin
		if rst = '0' then
			for i in output'range loop
				output(i) <= '0';
			end loop;					
		elsif rising_edge(clock) then
			output	<=	input;
		end if ;
	end procedure registery ;

what is the syntex for assigning to it std_logic (not vector)

thanks
 

I assume you're refering to the "input" paramater?

You can create a std_logic_vector from a std_logic simply by concatenating it with a null array

Code VHDL - [expand]
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signal sl : std_logic;
 
....
 
registery(clk, rst, ""&sl, op);
 

This is what i thought but i get this error:
(vcom-1451) Actual (infix expression) for formal "input" is not signal name.
Click to expand...
 

then you'll have to create a temprary signal to do it. 

Code VHDL - [expand]
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signal slv : std_logic_vector(0 downto 0);
 
slv(0) <= sl;
 

You may want to type "verror 1451" to learn about the error cause.

I guess you are using a VHDL 1987 settings that don't allow expressions in port assignments.
 

FvM said:
You may want to type "verror 1451" to learn about the error cause.

I guess you are using a VHDL 1987 settings that don't allow expressions in port assignments.
Click to expand...

The problem here is that its a procedure - and on a precedure object classes must match.
So while constants can be connected to anything, signals must connect to signals and variables must connect to variables.

The original concatenation I suggested creates a constant.
 

The compiler is set to vhdl 2008
It worked after i changed it to constant,

Still what about the output? (let's say i want to maintain std_logic)
 

Use named association in port instantiation and assign input and output signals explicitly.

Code VHDL - [expand]
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...
input(0) => sl,
ouput (0) => op
 

FvM said:
Use named association in port instantiation and assign input and output signals explicitly.

Code VHDL - [expand]
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...
input(0) => sl,
ouput (0) => op
Click to expand...

unlikely to work, as output from the procedure has no length, and is sized from the slv that is connected.
To the OP, you will need a slv signal to connect to - so you'll need a temporary signal to connect to, and then connect a single bit to your std logic.
 

unlikely to work
Click to expand...
Surprisingly, Modelsim accepts the partial association, both for procedures and components.
Quartus does for components, but doesn't support partial association for procedures.

Nevertheless, temporary signal is the safe way.
 

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