What is Lateral Bipolar Mode MOSFET?

Hi forums,
This paper: https://ieeexplore.ieee.org/document/1051939/ presents an overview of a MOSFET in laternal BiPolar mode combining properties of both BJT and MOSFET(if i understand it correctly).

* Can anyone explain it in a bit simplified manner on how it actually works?
* How is a Lateral BiPolar Mode MOSFET different from BiCMOS?
* What advantage/disadvantage Lateral layout has over vertical layout's of BJT's? In paper it's mentioned that in lateral layout we can make use of the CMOS parasitic BJT's, is this the only advantage?

Thanks!

Look at integrated MOSFET construction. Can't you see
the N, P, N structure (or P, N, P for PMOS)? There you
are.

Suppressing the BJT is job #1 for device design / process
development / layout groundrules definition. But every
decade somebody rediscovers some way to put the BJT
to use. And then generally gives up, because it's not a
very good transistor.

Lateral BJTs have only one good point, which is a
symmetric high blocking voltage. You saw them used for
this, specifically, in standard linear ICs for decades.
A lateral PNP was (1) a freebie, using the NPNs' implants
and (2) a way to get 30V input differential voltage in
a 30V process.

Lateral BJTs otherwise svck pretty badly especially
when it comes to low current beta rolloff (due to a
high base surface area and that the collector current
has to run along the underside of the base oxide
interface which nobody really cared to optimize for
traps / surface recombination velocity (especially
not CMOS process developers, for whom any kind
of recombination is generally a bonus).

"Love the one you're with" is about it. She's dumb
and ugly, but PhD supermodels rarely show up around
closing time.