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How to Optimize power with Design Compiler

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javierh.santiago

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Hello,

I am synthesizing combinational circuits with Design Compiler from Synopsys, and I would like to optimize each circuit for the delay, power, and area independently i.e. three netlist in total (one for each optimization in each component) . I am using following constrains for area and delay, but I don't know how to optimize for power yet. Can you advise how to do it?

Power:
"ANY ADVISE"?

Delay:
set_max_delay 0 -from [all_inputs] -to [all_outputs]

Area:
set_max_area 0.0 -ignore_tns

thanks
 

set_leakage_optimization true
set_dynamic_optimization true
read_saif -input your.saif -instance_name testbench/dut -auto_map_names
set compile_clock_gating_through_hierarchy true
compile_ultra -gate_clock
 

javierh.santiago said:
Hello,

I am synthesizing combinational circuits with Design Compiler from Synopsys, and I would like to optimize each circuit for the delay, power, and area independently i.e. three netlist in total (one for each optimization in each component) . I am using following constrains for area and delay, but I don't know how to optimize for power yet. Can you advise how to do it?

Power:
"ANY ADVISE"?

Delay:
set_max_delay 0 -from [all_inputs] -to [all_outputs]

Area:
set_max_area 0.0 -ignore_tns

thanks
Click to expand...

synthesis tools are notably bad at optimizing anything but timing. the SDC commands for max_area and max_power have been ignored for many years.
timing is always given the priority. once timing is met, then area and power are looked at. they are secondary in nature.

FYI, the way you are doing the timing optimization is correct but not necessarily good. you are asking the tool to try for an impossible timing. the tools sometimes realize the target is impossible and give up earlier than they should. sometimes some optimization tricks are never tried because of impossible targets.
 

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