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  1. #1
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    Design Constraints in Design Compiler

    Hello,

    I am doing synthesis for different RTL components (Combinational Circuits) with Design Compiler from Synopsys, and I would like to optimize for maximum performance in terms of power, area, and delay independently i.e. one netlist for each optimization (total 3 circuits for each component). I am using following constraints for delay and area, but I don't not how to do it for power yet. Do you know what are those constrains?


    AREA:
    set_max_area 0.0

    DELAY:
    set_max_delay 0 -from [all_inputs] -to [all_outputs]

    POWER:
    any advise???


    thanks

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  2. #2
    Junior Member level 1
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    Re: Design Constraints in Design Compiler

    The first tips:in order to same power you can use the clock gaiting tecquique by enabling it when you elaborate your design.
    In general, power isn't optimized at syntesis level but at design level by using some usefull advice.
    Then you can use the syntesis process to further optimize your design such as extract the switching activity from the simulator and back annotate to synopsys so that the syntetizer could better estimate the power consumption and try to optimize the node with higher switching activity with structure with less swa.
    The way to set constrain on power is from the menu:
    Attributes->Optimization Constraints->Design Constraints
    and set the maximum dynamic power etc.
    for other tips and command, please read the manual:
    http://eclass.uth.gr/eclass/modules/...tion/pwcug.pdf


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