Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso

Hi, I am currently doing a project related to mixed IC design, for the digital part is the Digital PWM Generator Module design using verilog coding, and for the analogue part is the AC-DC & DC-DC boost converter design using Cadence Virtuoso.

For the digital PWM Generator module, I am using the the Synopsys DC + ICC to complete the RTL to GDSII flow,
and for the analogue AC-DC & DC-DC boost converter module it is full custom designed using Cadence Virtuoso.

I am having trouble passing the LVS in Cadence Virtuoso when I streamed in the GDSII file obtained from the ICC. Can someone kindly provide the step by step to stream in GDSII file from ICC into Cadence Virtuoso, passing the LVS & DRC and finally integrate the digital and analogue part in Cadence Virtuoso?

Thanks

You have already done the stream out from Cadence as you are saying it is failing LVS when stream out from Cadence. What kind of LVS and DRC issues are you seeing?