# Non-overlapping clocks with a "envelope clock"

1. ## Non-overlapping clocks with a "envelope clock"

Hi Team
I am trying to design 8 phases non overlapping clocks with a pair of non_overlapping "envelope clocks" as depicted in the attached picture
The left side of the picture: The first 8 signals are the non-overlapping clocks and the last 2 (white and brown) clock signals are the envelope clocks. In other words, the envolope clock (white) should be "1" before the first clock phase(green) is "1" and remain the level after last clock phase (yellow) is one. However, it also have to be "0" before the next round of 8 phases.
The right side of the picture: The illustration of such a relationship.
All of the nonoverlapping is achieved by cross-coupled NOR with 2 inverters. The 8 phases non-overlapping clocks are achieved by johns counter
and the envelope signal is by a frequency divider of one if the flipflops as in the pic

BUT THE PHASE/DELAY RELATIONSHIP BETWEEN 2 ENVELOPE SIGNALS AND 8 PHASES CLOCKS IS BY HAND TUNED INVERTER DELAY UNITS.

Question:
Unlike the non-overlapping-ness is secured by the topology, the phase relationship between the 2 envelope signals and 8 phases clock is affected by process variations. In other words, one of the envelope signal may fail to cover the last clock phase or may cover the first clock phase of the next 8 phases round.

Is there a topology that I can use to secure the phase relationship between the 2 envelope signals and 8 phases clock as I desired?

Thank you!
Allen

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2. ## Re: Non-overlapping clocks with a "envelope clock"

Probably the reliable thing is to use rising/falling edges as a trigger to begin the next stage of the cycle.
1) Start by making the white pulse go high.
2) Use its rising edge as a trigger to run a circuit that counts-to-8-and-halt.
3) The falling edge of the yellow pulse triggers the red pulse to drop low.
4) That ends a cycle, and serves to trigger a new cycle.

Since you know about CD4022 then you know about 4017 decade counter IC. I believe it can be arranged do a count-to-8-and hold.

There is a method to create a brief delay immediately after an output changes state. Put a capacitor in series with the output. It produces a spike which can then be cleaned up with a logic gate or schmitt trigger.

3. ## Re: Non-overlapping clocks with a "envelope clock"

Probably the reliable thing is to use rising/falling edges as a trigger to begin the next stage of the cycle.
1) Start by making the white pulse go high.
2) Use its rising edge as a trigger to run a circuit that counts-to-8-and-halt.
3) The falling edge of the yellow pulse triggers the red pulse to drop low.
4) That ends a cycle, and serves to trigger a new cycle.
In this method, do you use the envelope signals as the anchor and generate 8 phases clock accordingly? Because my 8 phases clock is generated by johnson's counter, which connects the output node back to its input to form a loop. So for your step 2), do you suggest abandon my previous method(4022) and use 4017 instead?

Since you know about CD4022 then you know about 4017 decade counter IC. I believe it can be arranged to do a count-to-8-and hold.
I am unfortunately not familiar with the clock design and I tried to learn the 4017 as you suggested. It seems 4022 is already an octal counter. Can you please let me know why I should use a decade counter 4017 and modify it to be octal counter instead? Is there any benefit 4017 have over 4022?

There is a method to create a brief delay immediately after an output changes state. Put a capacitor in series with the output. It produces a spike which can then be cleaned up with a logic gate or schmitt trigger.
That's a great suggestion. Thank you! But can you please let me know how should I use this method in my circuit? Where in the circuit do i need the immediate delay in my clock generator?

Thanks again
Allen

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4. ## Re: Non-overlapping clocks with a "envelope clock"

It is all right to use 4022. The 4017 seems to be popular. I made a simulation which generates 8 pulses, and resets after 9 cycles. The reason is because your scope trace appears to have a space between the yellow and green pulses.

Following pulse #8 are capacitor-resistor-logic-gate networks. This demonstrates a method to create delayed events.
Many various combinations are possible which yield different waveforms. Whether resistor goes to ground, or capacitor to V+ or to ground, using buffer or invert gate, diode pointing away from input or toward input, etc.

If you wish to keep the 4022 then you can create a slight delay of the first pulse, by using the right kind of capacitor-resistor-diode network. This will give time for ending one envelope and beginning another.

5. ## Re: Non-overlapping clocks with a "envelope clock"

It's my bad that I did not make my point clear previously. The clock generator is a controlling block of my analog circuits, which demands 8 non-overlapping phases clocks spread evenly over each 8-phased-cycle. In other words, the distance of phase 8 to next phase 1 have to be equal to any phase n and phase n+1. So unfortunately, I don't have the luxury to add a delay gap as your simulated waveform after phase 8 and next phase 1.

So far, I am doubling the 4022 and create a 16 phases clock and only use the 1,3,5,7... phases and a toggle FF to see if I can add the envelop correctly. But unfortunately, the problem of uncertain delay between envelop and 8 phases clock remains.

Please let me know if you have any further suggestions. Anything helps

Thank you again
Allen

6. ## Re: Non-overlapping clocks with a "envelope clock"

Yes, a divide-by-2 FF is able to generate your red & white waveforms.
(One from Q output, the other from not-Q). That way you don't need a second octal counter.

Configure the FF to change state immediately at the falling edge of the yellow (8th) pulse. Or if unfeasible then at the rising edge of the green (1st). One or the other ought to work.

7. ## Re: Non-overlapping clocks with a "envelope clock"

That's exactly what I have done to get the waveform I attached.
But please correct me if I were wrong: The relationship of "envelope" is not secured by the topology. If the process variation caused a considerable additional delay in the circuit, the envelope signal could delay further and cover some of the green (first )signal of the next cycle?

Thanks
Allen

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8. ## Re: Non-overlapping clocks with a "envelope clock"

Since you wish to preserve an envelope characteristic then you need to create a direct relationship between the green pulse and the red/white waveforms. That is, make the one event dependent on the other happening first.

Therefore resume the clock immediately after the flip-flop changes its output.
You can attach steering diodes to Q and not-Q, so that one of them going high is able to send an Enable pin high.

Pause the clock after the yellow pulse ends. It is idle for a tiny fraction of a second.

Of course your other idea is feasible, to reduce the duty cycle of each pulse, so that you have an idle gap after the end. However it may also work if you simply ramp up the first pulse with a DCR network. This surely allows time to preserve the red/white envelope characteristic, yet you need not pause the clock. Therefore the 8 time intervals remain equal.

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