Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog Code: How to read count value when Trigger signal is high ?

Status
Not open for further replies.

AbinayaSivam

Member level 1
Joined
Jul 27, 2017
Messages
38
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
345
Hi,

I want to read the out value with the condition when the Trigger signal (Trig_SG) is high. I have tried with below code but i didnt got proper output. Please suggest me.
Code:
module Trigger_RTC
(
input clk_50,
//output Trig_SG,
output reg Final_out
);
reg out;
reg Trig_SG=1'b0;
always@(posedge clk_50)
begin
Trig_SG<=1'b1;

if(Trig_SG==1'b1)
begin
out<=out+1;
Final_out<=out;
end
else
   Final_out<=0;
end 
endmodule
 

What do you expect as "proper output"? According to your code, Trig_SG will be activated at the first clock edge after power on reset and stay permanently on. You should see this in a simulation.
 

Where is the source of the Trig_SG and "out value" signals? Are they from external module/pin or driven internally inside Trigger_RTC module?
Please give us more context about the function of this block. What do you want to do and what is the vicinity?

You want to read the "out value", but the "out value" is not an input for this module. Also Trig_SG is not an input - so it is confusing.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top