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Spartan6 project interacting with DDR SDRAM (implementation error during "MAP")

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FlyingDutch

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Spartan6 project interacting with DDR SDRAM (1 timing constraint not met)

Hello,

I am trying to implement project from this WWW page:

**broken link removed**

This is VGA framebuffer using DDR RAM (using the Spartan 6 MCB interface). This is my first project using DDR RAM, and I experienced difficulties.

I am using Mimas V2 Spartan 6 FPGA Development Board with DDR SDRAM. Here are links to producer site:

http://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram

http://numato.com/docs/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram/

Here is packed with zip full project for Xilinx "ISE Webpack" (version 14.7) :

View attachment FrameBuffer01.zip

After synthesis and implementation I have one error - in "Timing constraints" there is one error "1 Failing constraint".

Here is ending part of "Post-PAR Static Timing Report":

Code:
Derived Constraint Report
Derived Constraints for Inst_mem_wrapper/u_mem32/memc3_infrastructure_inst/sys_clk_ibufg
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|Inst_mem_wrapper/u_mem32/memc3_|     10.000ns|      3.334ns|     17.652ns|            0|            1|            0|        19616|
|infrastructure_inst/sys_clk_ibu|             |             |             |             |             |             |             |
|fg                             |             |             |             |             |             |             |             |
| Inst_mem_wrapper/u_mem32/memc3|     10.000ns|      0.952ns|      1.499ns|            0|            0|            0|            0|
| _infrastructure_inst/clk_2x_0 |             |             |             |             |             |             |             |
|  Inst_mem_wrapper/u_mem32/c3_s|     10.000ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  ysclk_2x                     |             |             |             |             |             |             |             |
| Inst_mem_wrapper/u_mem32/memc3|     10.000ns|      0.952ns|      1.499ns|            0|            0|            0|            0|
| _infrastructure_inst/clk_2x_18|             |             |             |             |             |             |             |
| 0                             |             |             |             |             |             |             |             |
|  Inst_mem_wrapper/u_mem32/c3_s|     10.000ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  ysclk_2x_180                 |             |             |             |             |             |             |             |
| Inst_mem_wrapper/u_mem32/memc3|     13.333ns|     23.536ns|          N/A|            1|            0|        19616|            0|
| _infrastructure_inst/mcb_drp_c|             |             |             |             |             |             |             |
| lk_bufg_in                    |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_50
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_50         |    7.852|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 1  Score: 1275  (Setup/Max: 1275, Hold: 0)

Constraints cover 19616 paths, 0 nets, and 2128 connections

Design statistics:
   Minimum period:  23.536ns{1}   (Maximum frequency:  42.488MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Wed Aug 15 17:15:56 2018 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 202 MB

I would like to ask if changing frequency to 50 MHz (from 100 MHz) of top entity would be proper solution?

Regards

There is one error in "top_level.ucf" file. Should be:

Code:
NET  "mcb3_dram_ck"              LOC = G3      | IOSTANDARD = DIFF_MOBILE_DDR;
NET  "mcb3_dram_cke"             LOC = H7      | IOSTANDARD = MOBILE_DDR;

is
Code:
NET  "mcb3_dram_ck"              LOC = G3      | IOSTANDARD = DIFF_MOBILE_DDR;
NET  "mcb3_dram_cke"             LOC = H7      | IOSTANDARD = DIFF_MOBILE_DDR;

Sorry for that error.
 
Last edited:

Re: Spartan6 project interacting with DDR SDRAM (implementation error during "MAP")

Hi,

I would like to ask if changing frequency to 50 MHz (from 100 MHz) of top entity would be proper solution?
Why don't you modify your timing constraint to test it on your own?

Klaus
 

Re: Spartan6 project interacting with DDR SDRAM (implementation error during "MAP")

If changing frequency to 50 MHz (from 100 MHz) also meets your functional requirements (2x slower reading inputs and driving outputs) - it is fine.

I don't have ISE 14.7, so I can't see your project in that IDE, but I have looked into top_level.syr file where is a Timing Report.
The main problem is inside Inst_mem_wrapper where Total Delay is 5.758ns (Levels of Logic = 5) and requirement is circa 4.319ns.
Is it some customisable IP core? I suggest to add pipeline stages inside that Inst_mem_wrapper.

You can also open the PlanAhead (if you have a license) for timing analysis after implementation, what I always highly recommend.

The path is as follows:
Code:
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            11   0.447   1.130  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_5 (Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_5)
     LUT4:I0->O            2   0.203   0.845  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_338_o22 (Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_338_o21)
     LUT5:I2->O            2   0.205   0.845  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_338_o23 (Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_338_o)
     LUT5:I2->O            4   0.205   0.684  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd3-In41_SW0 (N18)
     LUT6:I5->O            1   0.205   0.684  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd3-In41_SW1 (N67)
     LUT6:I4->O            3   0.203   0.000  Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd1-In4 (Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd1-In)
     FDR:D                     0.102          Inst_mem_wrapper/u_mem32/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd1
    ----------------------------------------
    Total                      5.758ns (1.570ns logic, 4.188ns route)
                                       (27.3% logic, 72.7% route)
 
Re: Spartan6 project interacting with DDR SDRAM (implementation error during "MAP")

I would verify that the DDR coregen constraints were actually applied to the design. Check the report files for any warnings about constraints not being applied.
 

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