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Porting Verilog design from Quartus II Lite to LabVIEW

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tahirsengine

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Hi,
Hope that post finds you well.
I am in a fix.
I have many many designs, all made in Verilog. I also know only Verilog(No experience with VHDL).
Now I need to port that designs within LabVIEW.
I have only Quartus II Lite software with me for HDL design entry and testing.

Now, Quartus II doesn't produce edif or edf files, that may be ported to LabVIEW FPGA.
If I use Xilinx ISE free version, than it doesn't let me simulate designs.

Is there any way I may produce some files, using either Quartus II Lite that I may port to LabVIEW?

I know, the problem is complicated, but I trust you guys.

All suggestions are welcome.

Regards


++Tahir
 

Please explain which kind of circuits you want to import to LabView FPGA? EDIF is a netlist description file format, don't see how it should be related to Verilog HDL.

Verilog designs can be simulated in free ModelSim Altera Starter Edition.
 

FvM said:
Please explain which kind of circuits you want to import to LabView FPGA? EDIF is a netlist description file format, don't see how it should be related to Verilog HDL.

Verilog designs can be simulated in free ModelSim Altera Starter Edition.
Click to expand...

Thanks for replying.
Actually problem with me is that I have just free versions of both Xilinx Vivado and Intel Quartus II Lite.
The only licence I have is of Labview.
Now, Labview only accepts either VHDL or EDIF files as an input, but I don't know VHDL.
Although I can simulate designs in Quartus, but how will I port my Verilog in LabVIEW. That's the problem. So for that I need to use Xilinx Vivado.
I am needing a solution in which I am porting my Verilog design directly to LabVIEW.

Regards

++Tahir
 

Yes, there is a simulator with Vivado package.
 

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