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  1. #1
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    Weird synthesis error (Xilinx, Verilog)

    Dear all.

    Im currently synthesizing a design using Xilinx ISE. 14.7

    Based on the warning below, it says that ALL the sub module is
    unconnected.

    Code dot - [expand]
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    WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in 
    block <A>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block 
    <pe_block[0].pe.pe0>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block 
    <pe_block[0].pe.pe0>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block 
    <pe_block[0].pe.pe0>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block 
    <pe_block[0].pe.pe0>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in 
    block <A>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block 
    <pe_block[1].pe.pe1>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block 
    <pe_block[1].pe.pe1>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block 
    <pe_block[1].pe.pe1>.
    It will be removed from the design.
    WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block 
    <pe_block[1].pe.pe1>.
    It will be removed from the design.
     
     
     
    WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaH> 
    of block <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaIx> 
    of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. 
    Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaV> 
    of block <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaH> 
    of block <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaIx> 
    of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. 
    Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaV> 
    of block <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance 
    <pe_block[0].pe.pe0/A/CompInterA> of block <Sync_Rst_CompInter> are 
    unconnected in block <SystolicArrayNovelty2>. Underlying logic will be 
    removed.
    WARNING:Xst:2973 - All outputs of instance 
    <pe_block[1].pe.pe1/A/CompInterA> of block <Sync_Rst_CompInter> are 
    unconnected in block <SystolicArrayNovelty2>. Underlying logic will be 
    removed.
    WARNING:Xst:2973 - All outputs of instance 
    <pe_block[0].pe.pe0/DeltaIy/DeltaLeftSubtract> of block 
    <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.
    WARNING:Xst:2973 - All outputs of instance 
    <pe_block[1].pe.pe1/DeltaIy/DeltaLeftSubtract> of block 
    <Sync_Rst_TWO_Input_Sub> are unconnected in block 
    <SystolicArrayNovelty2>. Underlying logic will be removed.


    This the verilog code for the top module that I currently synthesis.


    Code Verilog - [expand]
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    module 
    SystolicArrayNovelty2(Clk,Rst,SubSec,QueSec,PDeltaH,PreDeltaIy,SubSecOut 
    );
     
        parameter ComputeDataWidth        = 8;
        parameter PE = 2; //LENGTH
        parameter QC = 2; //QC bit size
     
        input                                           Clk,Rst;
        input                                   [QC-1:0]  SubSec;
        input             wire              [(PE*QC)-1:0]  QueSec;
        input                        [ComputeDataWidth-1:0] 
    PreDeltaH,PreDeltaIy;
        output                                 [QC-1:0]     SubSecOut;
     
        wire                    [ComputeDataWidth-1:0] h         [PE-1:0];
        wire                    [ComputeDataWidth-1:0] l         [PE-1:0];
       wire                                [PE*3-1:0] SSout;
     
        genvar i;
     
        generate
            for (i=0; i < PE; i = i + 1)
                begin : pe_block
                    if (i == 0)                       //first processing 
    element in auto-generated chain
                        begin:pe
                            ProcessingElementNovelty2 pe0
                                (  .Clk                       (Clk),
                                    .Rst                       (Rst),
                            .SS                        (SubSec[1:0]),
                            .QC                        (QueSec[1:0]),
                                .PreDeltaH                 (PDeltaH),
                            .PreDeltaIy                (PreDeltaIy),
                                    .DelH                      (h[i]),
                            .DelIy                     (l[i]),
                                    .SS_Out                    (SSout[1:0])
                           );
                        end
                    else         //processing elements other than first one
                        begin:pe
                      ProcessingElementNovelty2 pe1
                                (   .Clk                       (Clk),
                                     .Rst                       (Rst),
                             .SS (SSout[(2*i)-1:(2*i)-2]),
                             .QC (QueSec[(2*i)+1:(2*i)]),
                                 .PreDeltaH                 (h[i-1]),
                             .PreDeltaIy                (l[i-1]),
                                     .DelH                      (h[i]),
                             .DelIy                     (l[i]),
                                     .SS_Out                    (SubSecOut)
                               );
                        end
                end
        endgenerate
    endmodule


    AND this the submodule verilog code based on the above top module and
    RTL diagram with no warning (attached).



    Code Verilog - [expand]
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    `timescale 1ns / 1ps
    module ProcessingElementNovelty2(Clk,Rst,SS,QC,PreDeltaH,PreDeltaIy,
                                             DelH,DelIy,SS_Out);
     
        parameter ComputeDataWidth        = 8;
     
        localparam
        N_A         = 2'b00,        //nucleotide "A"
        N_C         = 2'b01,        //nucleotide "C"
        N_G         = 2'b10,        //nucleotide "G"
        N_T         = 2'b11;        //nucleotide "T"
     
       input                                           Clk,Rst;
        input                                       [1:0]  SS,QC;
       input             signed    [ComputeDataWidth-1:0] PreDeltaH,PreDeltaIy;
        output          signed     [ComputeDataWidth-1:0]     DelH,DelIy;
       output                                       [1:0]  SS_Out;
     
        wire           signed    [ComputeDataWidth-1:0] a,DelIx,DelV;
     
        IntermediateA
                    #(    .ComputeDataWidth    (ComputeDataWidth))
        A
                    (
                       .Rst                        (Rst),
                       .SUBJECT_SEQUENCE           (SS),
                       .QUERY_CHARACTER            (QC),
                        .DelIx_i_1_j                (DelIx),
                        .DelIy_i_j_1                (PreDeltaIy),
                        .SCORE_InterA               (a),
                        .SUBJECT_SEQUENCE_OUT       (SS_Out)
                    );
     
        Sync_Rst_TWO_Input_Sub
                    #(    .ComputeDataWidth    (ComputeDataWidth))
        DeltaH
                    (
                        .Clk                         (Clk),
                        .Rst                     (Rst),
                       .A                              (a),
                        .B                              (DelV),
                        .AdditionOUT                 (DelH)
                    );
     
        Sync_Rst_TWO_Input_Sub
                    #(    .ComputeDataWidth    (ComputeDataWidth))
        DeltaV
                    (
                        .Clk                         (Clk),
                        .Rst                     (Rst),
                       .A                              (a),
                        .B                              (PreDeltaH),
                        .AdditionOUT                 (DelV)
                    );
     
        DelTop
                    #(    .ComputeDataWidth    (ComputeDataWidth))
        DeltaIx
                    (    .Clk                        (Clk),
                       .Rst                        (Rst),
                        .InterA                         (a),
                        .PreDelH                       (PreDeltaH),
                        .SCORE_DelTop               (DelIx)
                    );
     
        DelLeft
                    #(    .ComputeDataWidth    (ComputeDataWidth))
        DeltaIy
                    (
                        .Clk                        (Clk),
                       .Rst                        (Rst),
                        .InterA                         (a),
                       .PreDelIy_i_j_1             (PreDeltaIy),
                        .PreDelV                       (DelV),
                        .SCORE_DelLeft              (DelIy)
                    );
     
    endmodule


    Did I wrote the coding wrong?

    Thank you very much
    Last edited by BradtheRad; 13th August 2018 at 02:30. Reason: Added formatted window

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  2. #2
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    Re: Weird synthesis error (Xilinx, Verilog)

    From all the warnings, I cannot see any of the port names listed in the warnings. Are you sure you compiled the correct code?



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  3. #3
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    Re: Weird synthesis error (Xilinx, Verilog)

    Yup. The warnings is reported from the complied top module.
    The ports for the top module is correctly connected (attached).
    The warnings mentioned previously is about the sub module.
    From what I can see, the compiler cant detect my submodule (attached) because there were no error for compiling the sub module it self.
    Last edited by dayana42200; 13th August 2018 at 09:45. Reason: Left images



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  4. #4
    Advanced Member level 5
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    Re: Weird synthesis error (Xilinx, Verilog)

    Im still not quite sure what you're asking. If you know you unconnected component ports, then you should expect these warnings?
    Your image shows only SubSecOut connected.



  5. #5
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    Re: Weird synthesis error (Xilinx, Verilog)

    Its ok for me the other two output is unconnected

    But the schematic diagram should detect the sub module

    Click image for larger version. 

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