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    Need some tutorial for golden netlist flow

    I'm a beginner of ASIC. Recently I have complete the RTL coding in FPGA, now I want to transplant it to ASIC. But there is no whole flow for getting golden netlist. If there has any resources for it?


    btw,it's better if the resources using Genus or RTL compiler.

    Thanks a lot

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    Re: Need some tutorial for golden netlist flow

    As per my understanding, golden is just a version at a given stage of an ASIC design flow.
    FPGA enthusiast!



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  3. #3
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    Re: Need some tutorial for golden netlist flow

    Quote Originally Posted by smsskil View Post
    I'm a beginner of ASIC. Recently I have complete the RTL coding in FPGA, now I want to transplant it to ASIC. But there is no whole flow for getting golden netlist. If there has any resources for it?


    btw,it's better if the resources using Genus or RTL compiler.

    Thanks a lot
    I don't know what you are asking. Golden netlist?!

    Genus is the new version of rtl compiler. Use it if you have the license.
    Really, I am not Sam.



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  4. #4
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    Re: Need some tutorial for golden netlist flow

    Quote Originally Posted by ThisIsNotSam View Post
    I don't know what you are asking. Golden netlist?!

    Genus is the new version of rtl compiler. Use it if you have the license.
    I know. I mean that after RTL coding in FPGA, I need to do generic synthesis and technology synthesis. Then I need to verify synthesized netlist. Actually I dont know how the practical flow is running when people do the same things as I learn now.



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    Re: Need some tutorial for golden netlist flow

    Quote Originally Posted by smsskil View Post
    I know. I mean that after RTL coding in FPGA, I need to do generic synthesis and technology synthesis. Then I need to verify synthesized netlist. Actually I dont know how the practical flow is running when people do the same things as I learn now.
    I still don't understand what you are asking. It seems you are generically asking what an ASIC flow looks like. If that is what you are asking, it goes logic synthesis -> placement -> CTS -> routing -> sign-off. Lots of optimisations and checks along the way, of course.

    As to verifying the synthesised netlist, we don't do that anymore. We do thorough verification of the RTL, and some simple simulation of the netlist after. Mostly for connectivity checks, no actual design features are verified.
    Really, I am not Sam.



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