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  1. #1
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    how to include a module in another module?

    Hi all

    I wrote the following code (comparator.v and test_module.v), test_module is fairly simple. It just try to include comparator.v.

    However, when I try to compile the test_module.v, it reports the following errors. Can anyone help on the issue? Basically I am trying to include sub module using command "include", but I seems to have trouble on it.

    Thank you very much.

    ncverilog(64): 15.20-s022: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
    file: test_module.v
    module comparator(stag,ptag,tag_equal);
    |
    ncvlog: *E,EXPENM (comparator.v,1|5): expecting the keyword 'endmodule' [12.1(IEEE)].
    (`include file: comparator.v line 1, file: test_module.v line 2)
    module worklib.test_module:v
    errors: 1, warnings: 0
    endmodule // test_module
    |
    ncvlog: *E,EXPMPA (test_module.v,3|8): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
    Total errors/warnings found outside modules and primitives:
    errors: 1, warnings: 0
    ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).



    test_module.v

    Code:
    module test_module();
    `include "comparator.v"
    endmodule // test_module


    comparator.v

    Code:
    module comparator(stag,ptag,tag_equal);
      parameter n=16;
      input [n-1:0] stag,ptag;
      
      output        tag_equal;
    
      reg           tag_equal;
      
      integer       i;
    
    //   initial begin
    //   tag_equal<=1'b1;
    //   end
      
      always @(stag or ptag)
      
        tag_equal=!(stag^ptag);
    
    endmodule

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    Re: how to include a module in another module?

    You seem to misunderstand the purpose of Verilog `include statement. It's just including code text, if the merged text doesn't comply with Verilog syntax rules, it causes an error. Multiple modules in a single file must be not nested, they can be placed one after the other.

    Include is mainly used for common constant, variable and type definition. I guess your intention should be implemented by module instantiation.



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    Re: how to include a module in another module?

    Thanks FvM.

    In this case, can you please provide a solution?

    I know if I remove the include module statement, and then compile as

    ncverilog -c comparator.v test_module.v, it will pass, but I would like to keep both modules in a single verilog file. In another word, how can we have multi module definition in one file? Or it has to be in different module definition file?


    thank you very much for your help!

    Best regards,

    Brian


    Quote Originally Posted by FvM View Post
    You seem to misunderstand the purpose of Verilog `include statement. It's just including code text, if the merged text doesn't comply with Verilog syntax rules, it causes an error. Multiple modules in a single file must be not nested, they can be placed one after the other.

    Include is mainly used for common constant, variable and type definition. I guess your intention should be implemented by module instantiation.



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    Re: how to include a module in another module?

    A module you want to instantiate
    Code:
    module a (
      input x,
      output y
    );
    
      assign y = x;
    endmodule
    The module instantiation in another module e.g.
    Code:
    module b (
      input m,
      output n
    );
      a  a_inst (
        .x (m),
        .y (n)
      );
    endmodule
    Like I said in your other thread, get and read a Verilog book. This is usually discussed in the first chapter.

    - - - Updated - - -

    If you want them in the same file:
    Code:
    module a (
      input x,
      output y
    );
      assign y = x;
    endmodule
    
    module b (
      input m,
      output n
    );
      a  a_inst (
        .x (m),
        .y (n)
      );
    endmodule
    but having multiple modules in one file is a bad practice. The general rule you should follow is one module per file.



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    Re: how to include a module in another module?

    What are the downsides to multiple modules in a file?

    Convenient sharing of individual modules is one but when multiple modules are closely related and unlikely to be used stand-alone I don't see this causing an issue.

    At this point I often allow myself multiple modules in a file and often include their testbench in that file as well.



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    Re: how to include a module in another module?

    Quote Originally Posted by asdf44 View Post
    What are the downsides to multiple modules in a file?

    Convenient sharing of individual modules is one but when multiple modules are closely related and unlikely to be used stand-alone I don't see this causing an issue.

    At this point I often allow myself multiple modules in a file and often include their testbench in that file as well.
    that is generally considered bad practice.
    Really, I am not Sam.



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    Re: how to include a module in another module?

    Yes, and the question is why?



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    Re: how to include a module in another module?

    Quote Originally Posted by asdf44 View Post
    Yes, and the question is why?
    It relates to synthesis, you want the file name to match the module name. You can't get that with two modules on the same file.

    It also relates to how companies divide the labor internally, ownership of code, coding styles. There is no technical reason, it's just good practice versus bad practice.
    Really, I am not Sam.



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    Re: how to include a module in another module?

    Quote Originally Posted by ThisIsNotSam View Post
    It relates to synthesis, you want the file name to match the module name. You can't get that with two modules on the same file.

    It also relates to how companies divide the labor internally, ownership of code, coding styles. There is no technical reason, it's just good practice versus bad practice.
    besides this it also impacts reuse when you are adding some_module_xyz.v when you want a module_abc in your design, build scripts get ugly and no longer make sense, and you end up synthesizing more stuff than you need to as synthesis won't know you don't need a 200K gate module in your design because you didn't use it and only wanted to use the 5K gate module that was also in the same file.



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    Re: how to include a module in another module?

    If you want to include a verilog code, then remove module and endmodule from comparator.v. That way your include will be plain Verilog code as part of test_module. It will work fine in synthesis and simulation. However, that being said, downside is when you go to any simulation tool like Verdi, there will be no scope definition or declaration of comparator.v. It becomes difficult to navigate. As already being pointed here instantiating is best solution.

    Thanks.



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    Re: how to include a module in another module?

    Hi

    It does not really work. Thank you for your comments.

    Quote Originally Posted by swabhi812 View Post
    If you want to include a verilog code, then remove module and endmodule from comparator.v. That way your include will be plain Verilog code as part of test_module. It will work fine in synthesis and simulation. However, that being said, downside is when you go to any simulation tool like Verdi, there will be no scope definition or declaration of comparator.v. It becomes difficult to navigate. As already being pointed here instantiating is best solution.

    Thanks.
    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    besides this it also impacts reuse when you are adding some_module_xyz.v when you want a module_abc in your design, build scripts get ugly and no longer make sense, and you end up synthesizing more stuff than you need to as synthesis won't know you don't need a 200K gate module in your design because you didn't use it and only wanted to use the 5K gate module that was also in the same file.
    Make sense, thank a lot!

    - - - Updated - - -

    Quote Originally Posted by ThisIsNotSam View Post
    It relates to synthesis, you want the file name to match the module name. You can't get that with two modules on the same file.

    It also relates to how companies divide the labor internally, ownership of code, coding styles. There is no technical reason, it's just good practice versus bad practice.

    Thank you, it is something new to me. What you said totally make sense. Thanks a lot.

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    A module you want to instantiate
    Code:
    module a (
      input x,
      output y
    );
    
      assign y = x;
    endmodule
    The module instantiation in another module e.g.
    Code:
    module b (
      input m,
      output n
    );
      a  a_inst (
        .x (m),
        .y (n)
      );
    endmodule
    Like I said in your other thread, get and read a Verilog book. This is usually discussed in the first chapter.

    - - - Updated - - -

    If you want them in the same file:
    Code:
    module a (
      input x,
      output y
    );
      assign y = x;
    endmodule
    
    module b (
      input m,
      output n
    );
      a  a_inst (
        .x (m),
        .y (n)
      );
    endmodule
    but having multiple modules in one file is a bad practice. The general rule you should follow is one module per file.
    Thank you, just curious. If the two modules need to be in the same file, it seems that the two modules have to have the same input and output.



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    Re: how to include a module in another module?

    Thank you, just curious. If the two modules need to be in the same file, it seems that the two modules have to have the same input and output.
    Not at all. Each module is compiled independently, they can be related or not. Restart reading your Verilog text book.



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    Re: how to include a module in another module?

    It does not really work. Thank you for your comments.
    You didn't tell yet what you want to achieve. Having a module test_module() with no in- and output ports suggests you want to write a test bench. It needs to generate input signals for the design under test and possibly displays or checks the output.



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    Re: how to include a module in another module?

    What I suggested should work. I have seem code similar to what I said in my company few times. Let me know if you need more clarifications.



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