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Noise analysis in cmos inverter using ngspice

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smita1811

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I have created a file for cmos inverter using ngspice.

The ngspice netlist is as follows:
Code: 
*******************************************
.include technologyfiles/16nmLP.pm ; LP stands for Low Power. It has high tox and high vth values. nmoslp and pmoslp refers to this file
.param psu = 0.9
.param len = 16n
.param wpmos=250n wnmos=100n 

vsupply vdd 0 {psu}
vgnd vss 0 0V
vin1 v1 vss dc 0 ac 0.9V sin(0V 0.9V 100MegHz 20ns 0)

*output inverter
Mp1 vout v1 vdd vdd pmoslp l={len} w={wpmos} ; pmos
Mn1 vout v1 vss vss nmoslp l={len} w={wnmos}; nmos 
Cload vout vss1 200f
vdc0 vss1 vss dc 0V
.End
***********************************

For noise analysis I have done the following steps:
>ngspice filename
>noise v(vout) vin1 dec 10 1MegHz 100MegHz
>display
>print inoise_total, onoise_total

The values for inoise_total is 1.032053e-03
The values for onoise_total is 1.217160e-14

I an confused about that the equivalent input noise is greater than the integrated output noise. Are the results feasible? What mistake am i doing?
Please help me.
 

Your are biasing the inverter input with 0 volt, resulting in effectively no gain.
 

FvM said:
Your are biasing the inverter input with 0 volt, resulting in effectively no gain.
Click to expand...


After providing the following input:
vin1 v1 vss ac 0.9V sin(0V 0.9V 100MegHz 20ns 0)

and doing the noise analysis using:
noise v(vout) vin1 dec 10 1MegHz 100MegHz

I have got the following results:
ngspice 4 -> print inoise_total
inoise_total = 1.294150e-03
ngspice 5 -> print onoise_total
onoise_total = 1.841768e-08

Query1. In the results inoise_total is very very large than onoise_total?
Query2. Does the noise analysis depend upon the magnitude of the ac input ?
 

You really need to read about SPICE analysis methods and setup for noise analysis.

Noise analysis is a small signal AC analysis, it doesn't use e.g. sin() source which is only for transient (large signal) analysis.

Small signal analysis (gain, frequency response, noise) of nonlinear circuits, e.g. amplifiers depends on suitable bias point. As a first guess, you can set Vin1 DC level to vdd/2. Depending on the MOSFET asymmetry, you may want to adjust the bias level to get vdd/2 DC output bias. Or use a self biasing test setup with DC feedback.

In any case, you should check the operation point after setting inverter bias.
 

Thanku so much.
Please clarify me about how to perform the noise analysis of digital cmos e.g domino logic which has more than one inputs and one clocked input.
Thanks
 

What should be the purpose? Noise analysis makes only sense for inverter used as linear amplifier, I suppose.
 

FvM said:
What should be the purpose? Noise analysis makes only sense for inverter used as linear amplifier, I suppose.
Click to expand...
I have read few papers on cmos domino logic which talks about the immunity of noise. So I want to compare those domino logic w.r.t noise immunity. Thus, I was trying to simulate the circuits for noise analysis.
 
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