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how to print integer in the verilog module

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liletian

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Hi All

I write the following module comparator, In the testbench, I would like to monitor integer i, when I try to print out the interger using the following statement, it does not work. Is there a way to keep track of the interger in the testbench?

Thank you very much,



Code Verilog - [expand]
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module comparator(stag,ptag,tag_equal);
   parameter n=16;
   input [n-1:0] stag,ptag;
   
   output        tag_equal;
 
   reg           tag_equal;
   
   integer       i;
 
//   initial begin
//   tag_equal<=1'b1;
//   end
   
   always @(stag or ptag)
     for(i=n-1;i>=0;i=i-1)
       begin: sweep
          if((stag[i]^ptag[i])) 
            begin           
               tag_equal<=1'b0;
//             break;
               
//             disable sweep;
            end
          else tag_equal<=1'b1;
       end
endmodule
 
 
  module test_comparator();
 
   parameter n=16;
   
   reg [n-1:0] A,B;
 
   wire        tag_equal;
 
   comparator #(n) com(.stag(A),.ptag(B),.tag_equal(tag_equal));
 
   initial begin
 
      $monitor($stime,  "  stag=%h,ptag=%h,tag_equal=%b, i=%b", A,B,tag_equal,com.i);
 
      #10;
 
      A=16'h000A;
      B=16'h000B;
 
      #10;
     A=16'h000B;
      B=16'h000B;
   end // initial begin
   endmodule

 
Last edited by a moderator:

I think only by putting a $display inside the for loop. A for loop in Verilog behaves differently than a for loop in programming languages. It's used to reduce the amount of replicated code. Once either stag or ptag changes the always block is entered and the for loop unrolls in 0 simulation time (meaning changes in i are never seen outside the always block)

In your case the for loop is unrolled to compare each bit of the vectors stag with ptag and setting tag_equal if any bit of the vectors match.
e.g.
if stag = 1011101 and ptag = 0100110
Code:
1011101
0100110
    ^ matches so tag_equal = 1
I wonder if this is really what you want to do here...I suspect it might not be what you expected.

Given what your code does it would be easier if you just wrote this:
Code:
assign tag_equal = !(stag == ~ptag);
i.e. if stag and ptag are bit-wise inverted from each other then the tag_equal is 0, otherwise it's 1
 

Hi Ads-ee

Thank you very much for your message.

It works if I add a display statement in the module itself.

About your comments, so in the verilog, for loop will be unroll at the beginning, it does not work as in program language. Is there any reading about this part?

If I remove the comments in the previous code (comparator module code)

disable sweep; (it was commented out in the original code, this one is used to stop the loop once one bit are not the same, then the output is expected to be zero),

the if the two value are not the same, the simulated output is "z" instead of zero, how can we understand this output results?

When the two values are the same, the output is 1 as expected.

Thank you very much for your help.

Best regards,

Brian

I think only by putting a $display inside the for loop. A for loop in Verilog behaves differently than a for loop in programming languages. It's used to reduce the amount of replicated code. Once either stag or ptag changes the always block is entered and the for loop unrolls in 0 simulation time (meaning changes in i are never seen outside the always block)

In your case the for loop is unrolled to compare each bit of the vectors stag with ptag and setting tag_equal if any bit of the vectors match.
e.g.
if stag = 1011101 and ptag = 0100110
Code:
1011101
0100110
    ^ matches so tag_equal = 1
I wonder if this is really what you want to do here...I suspect it might not be what you expected.

Given what your code does it would be easier if you just wrote this:
Code:
assign tag_equal = !(stag == ~ptag);
i.e. if stag and ptag are bit-wise inverted from each other then the tag_equal is 0, otherwise it's 1
 

You might be getting z because stag and ptag don't have a stag[16] and a ptag[16] bit as they are both defined as [n-1:0] and you defined n as 16. As your for loop uses i=n;i>=0;i=i++ as the start;end;increment values the first i is 16 and it doesn't exist. Not sure why it wouldn't affect the case where the values match though.

Still not sure why you would even write code like this it is probably the worst code I've seen for doing a compare in Verilog.

Verilog compare that most coders would use.

Code Verilog - [expand]
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assign tag_equal = (stag == ptag);
// or you could use this (but I prefer the previous less code to type)
assign tag_equal = (stag == ptag) ? 1'b1 : 1'b0;


this will works regardless of the value of n you use.

- - - Updated - - -

Update:

I was curious about the Z's you claim occur in the simulation of your code. I just ran your code from post #1 in modelsim and there are no Z's anywhere in the simulation, there are X's at the beginning of the simulation for ten time steps before anything is applied to the A and B inputs.
 

Hi ads-ee

Thank you very much for your reply. The simulator is ncverilog.

Here is my simulation results. "i" is actually 15 instead of 16 (I was using i=n-1 in my code). As you can see, at time 10, the result is x.

Yes, there have a simple way to do the comparator as you suggested ( tag_equal=!(stag^ptag);). I am just curious why there has x in the output in the current code.


One more question is "is "disable sweep;" synthesizerble?

Thank you very much,

Brian

ncsim> run
0 stag=xxxx,ptag=xxxx,tag_equal=x, i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
i=00000000000000000000000000001111
i=00000000000000000000000000001110
i=00000000000000000000000000001101
i=00000000000000000000000000001100
i=00000000000000000000000000001011
i=00000000000000000000000000001010
i=00000000000000000000000000001001
i=00000000000000000000000000001000
i=00000000000000000000000000000111
i=00000000000000000000000000000110
i=00000000000000000000000000000101
i=00000000000000000000000000000100
i=00000000000000000000000000000011
i=00000000000000000000000000000010
i=00000000000000000000000000000001
i=00000000000000000000000000000000
10 stag=000a,ptag=000b,tag_equal=x, i=11111111111111111111111111111111
i=00000000000000000000000000001111
i=00000000000000000000000000001110
i=00000000000000000000000000001101
i=00000000000000000000000000001100
i=00000000000000000000000000001011
i=00000000000000000000000000001010
i=00000000000000000000000000001001
i=00000000000000000000000000001000
i=00000000000000000000000000000111
i=00000000000000000000000000000110
i=00000000000000000000000000000101
i=00000000000000000000000000000100
i=00000000000000000000000000000011
i=00000000000000000000000000000010
i=00000000000000000000000000000001
i=00000000000000000000000000000000
20 stag=000b,ptag=000b,tag_equal=1, i=11111111111111111111111111111111
ncsim: *W,RNQUIE: Simulation is complete.


You might be getting z because stag and ptag don't have a stag[16] and a ptag[16] bit as they are both defined as [n-1:0] and you defined n as 16. As your for loop uses i=n;i>=0;i=i++ as the start;end;increment values the first i is 16 and it doesn't exist. Not sure why it wouldn't affect the case where the values match though.

Still not sure why you would even write code like this it is probably the worst code I've seen for doing a compare in Verilog.

Verilog compare that most coders would use.

Code Verilog - [expand]
1
2
3
assign tag_equal = (stag == ptag);
// or you could use this (but I prefer the previous less code to type)
assign tag_equal = (stag == ptag) ? 1'b1 : 1'b0;


this will works regardless of the value of n you use.

- - - Updated - - -

Update:

I was curious about the Z's you claim occur in the simulation of your code. I just ran your code from post #1 in modelsim and there are no Z's anywhere in the simulation, there are X's at the beginning of the simulation for ten time steps before anything is applied to the A and B inputs.
 

Okay missed the -1 after the n.

The X's are because the values assigned to A and to B aren't done until after #10 time units have passed. As the two signals are not initialized to anything they are X until assigned the first time.

- - - Updated - - -

disable sweep is NOT synthesizable.

You really need to pick up a Verilog book and learn the language before you get in the habit of writing a bunch of code that may or may not synthesize.
 

Hi Ads-ee

Thank you very much for the reply and help. I greatly appreciate it. Can you recommend a good verilog book?

I read some books and realized what I need is to exercise.

Thank you very much for your help.

Brian

Okay missed the -1 after the n.

The X's are because the values assigned to A and to B aren't done until after #10 time units have passed. As the two signals are not initialized to anything they are X until assigned the first time.

- - - Updated - - -

disable sweep is NOT synthesizable.

You really need to pick up a Verilog book and learn the language before you get in the habit of writing a bunch of code that may or may not synthesize.
 

Don't really know if any of these will help you as I learned Verilog after having spent a significant portion of my career working on digital designs using 7400 series parts and drawing schematics to create FPGA designs.

First Verilog book I bought pretty much the only one I could find.
The Verilog Hardware Description Language, Thomas/Moorby

A nice out of print book that shows the synthesis results of code written in both Verilog/VHDL. I would consider it a good book to begin to understand what circuits your code produces.
HDL Chip Design, Smith

The most recent book I picked up which is just okay.
Verilog HDL, Palnitkar

The LRM 1800-2017 for SystemVerilog (a superset of Verilog) is available for free thru the IEEE GET program you will need to sign up on the IEEE website.
 

Hi ads-ee

Thank you very much, lots of useful information. I appreciate your help.


Don't really know if any of these will help you as I learned Verilog after having spent a significant portion of my career working on digital designs using 7400 series parts and drawing schematics to create FPGA designs.

First Verilog book I bought pretty much the only one I could find.
The Verilog Hardware Description Language, Thomas/Moorby

A nice out of print book that shows the synthesis results of code written in both Verilog/VHDL. I would consider it a good book to begin to understand what circuits your code produces.
HDL Chip Design, Smith

The most recent book I picked up which is just okay.
Verilog HDL, Palnitkar

The LRM 1800-2017 for SystemVerilog (a superset of Verilog) is available for free thru the IEEE GET program you will need to sign up on the IEEE website.
 

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