liletian
Full Member level 6
Hi All
I write the following module comparator, In the testbench, I would like to monitor integer i, when I try to print out the interger using the following statement, it does not work. Is there a way to keep track of the interger in the testbench?
Thank you very much,
I write the following module comparator, In the testbench, I would like to monitor integer i, when I try to print out the interger using the following statement, it does not work. Is there a way to keep track of the interger in the testbench?
Thank you very much,
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 module comparator(stag,ptag,tag_equal); parameter n=16; input [n-1:0] stag,ptag; output tag_equal; reg tag_equal; integer i; // initial begin // tag_equal<=1'b1; // end always @(stag or ptag) for(i=n-1;i>=0;i=i-1) begin: sweep if((stag[i]^ptag[i])) begin tag_equal<=1'b0; // break; // disable sweep; end else tag_equal<=1'b1; end endmodule module test_comparator(); parameter n=16; reg [n-1:0] A,B; wire tag_equal; comparator #(n) com(.stag(A),.ptag(B),.tag_equal(tag_equal)); initial begin $monitor($stime, " stag=%h,ptag=%h,tag_equal=%b, i=%b", A,B,tag_equal,com.i); #10; A=16'h000A; B=16'h000B; #10; A=16'h000B; B=16'h000B; end // initial begin endmodule
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