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In what part of the design flow is the resolution of an OASIS layout file defined?

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arpanb

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Does anyone know at what point in the IC design flow the resolution of the layout is defined (i.e., OASIS file)? I have encountered multiple resolutions for the same technology node from the same foundry (TSMC 7nm) with resolutions of 0.001, 0.0005, etc.

Thanks,
Arpan Bhattacherjee
****email address removed ****
 
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Does anyone know at what point in the IC design flow the resolution of the layout is defined (i.e., OASIS file)? I have encountered multiple resolutions for the same technology node from the same foundry (TSMC 7nm) with resolutions of 0.001, 0.0005, etc.

Thanks,
Arpan Bhattacherjee
****email address removed ****

for any ASIC chip, no database is generated before the chip is complete. so... at the end
for IP (standard cells, memories), a GDS/OASIS is generated when the IP is ready...

Your question confuses me. You seem to worry that the resolution being different is a problem. It's not.
 

Thanks for the reply. I'm trying to figure out who, what team, or which tool is defining the resolution of the CAD layout before the GDS/OASIS is generated. Perhaps my question was misleading with "design flow" -- I am actually referring to the compete IC design process, including post-manufacturing failure analysis and yield improvement. The resolution being different is a problem for certain applications in this area.

Thanks again.
-Arpan
 

Again, resolution problem is not a problem, you can convert to any resolution you want.

If the design is digital, most likely the tool is Innovus. At export time you can pick the database unit you want.
If dealing with IP, most likely the tool is Virtuoso. At export time you can pick the database unit you want.
 

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