arpanb
Newbie
Does anyone know at what point in the IC design flow the resolution of the layout is defined (i.e., OASIS file)? I have encountered multiple resolutions for the same technology node from the same foundry (TSMC 7nm) with resolutions of 0.001, 0.0005, etc.
Thanks,
Arpan Bhattacherjee
****email address removed ****
Thanks,
Arpan Bhattacherjee
****email address removed ****
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