How to calculate the overall phase noise for a clock (frequency) network?

Hi,

Could anyone please help me.

I am trying to work out the overall phase noise of a local oscillator for a radio frequency receiver design. I have a 10MHz TCXO with certain phase noise characteristics/specification. Then the output of this TCXO is fed into a PLL clock synthesizer to generate another frequency of 26MHz. The PLL clock synthesizer also has certain phase noise characteristics at 26MHz. Then this 26MHz frequency will be fed into another VCO to generate an RF frequency, say 2350MHz to feed a mixer for the signal down-conversion, which again has certain phase noise characteristics at that frequency.

My question is how do I determine the overall phase noise for the LO @2350MHz? Do I just use the phase noise characteristics of that VCO @2350MHz or do I also need to cascade the phase noise from both the TCXO and the PLL clock synthesizer?

Any help will be highly appreciated. Thanks in advance.


Best regards,

chilchil

In case of doubt, add the phase noise contributions. For an exact calculation, you need to consider the loop bandwidths of both PLLs. A bandwidth reduction may filter out some phase noise of previous stages, but only if the phase detector linear range isn't exceeded.

Generally, you probably want to get rid of the intermediate PLL, and try to copy the TXCO low phase noise to the microwave VCO using a large bandwidth PLL.

Hi FvM,

Thanks a lot for your reply. I will give a go using your suggested two approaches.

Regards,
chilchil

FvM said:

In case of doubt, add the phase noise contributions. For an exact calculation, you need to consider the loop bandwidths of both PLLs. A bandwidth reduction may filter out some phase noise of previous stages, but only if the phase detector linear range isn't exceeded.

Generally, you probably want to get rid of the intermediate PLL, and try to copy the TXCO low phase noise to the microwave VCO using a large bandwidth PLL.

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