PEX LVS ERROR: Ground Net not defined

Dear all,

I have designed a chip containing different blocks. Each block is DRC, LVS clean and parasitics have been extracted. At top level when I connect every blocks to each other, Calibre DRC and LVS is clean. The LVS shows exact match between schematic and layout. But When I do PEX to extract the parasitics, the LVS (inside PEX) is incorrect and it is referring to one of the blocks (which is a T-Gate) and 6 of this block have been used. It is indicating that TGATE block is not compared. Error: Ground net is missing in the layout.
However, all the ground of analog blocks have been connected to AGND! . And also in LVS options I have defined the name of the ground nets (AGND and VSS! for digital circuitry). Can any of you help me with this? I do thank you.

Regards,

Are you sure that LVS options in your PEX script (or config file) are same with the ones when you do only LVS ? My opinion is that, for the same layout, if LVS works fine and LVS within PEX is not, this can be only due to the difference in the given options ...

Also a layout which is LVS clean in a flat-run LVS, can show errors when LVS is run hierarchically based on how the layout is done ( if correct pin/lables are inserted in a different hierarchy.) Therefore those are electrically false-errors coming from not clean layout...

Rgrds,