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ISE xc2c64a, 2 output, phase.

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victor910

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I have this code for a frequency divider

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-----------------------------
begin
 
if (clk'event and clk='1') then
count <=count+1;
 
 
if (count = 0) then
tmp <= NOT tmp;
count <= 0;
 
end if;
tmp3 <= NOT tmp3 after 20 ns ;
 
end if;
 
clock_out <= tmp;
clock_out3 <= tmp3;
 
end process
--------------------------------------
But first and second output in same phase. why "after 20 ns" do not working?
please help me.
 
Last edited by a moderator:

But first and second output in same phase. why "after 20 ns" do not working?
Click to expand...

What is the period of clk?
What is your simulator resolution set to?
 

dpaul said:
What is the period of clk?
What is your simulator resolution set to?
Click to expand...
I do not use the simulator. testing on the real device checked outputs with an oscilloscope. it's always different only 1ns.

CLK = 45mhz
outputs both 22.5Mhz
the outputs are correct, but I wanna have one output more latest, for example, the latest 20ns compare to another output.
 

"after" is not a synthesisable construct, and will be removed when you compile it for the chip. It only applies to simulation to model net delays in a system.
 

First, thanks for this information. You are saving a lot time for me.
Second, how to make little latency for second output in ”real life”.
 

victor910 said:
First, thanks for this information. You are saving a lot time for me.
Second, how to make little latency for second output in ”real life”.
Click to expand...

Use a register (or several for a longer delay - a shift register)
 

I’m absolutely noob about this, please give me an example code.
 

Second, how to make little latency for second output in ”real life”.
Click to expand...
You may use the Xilinx primitive "ODELAY". Using delay tap settings, an i/p signal can be delayed by a desired amount which appears at the o/p of the ODELAY. The Xilinx ISE documentation on ODELAY should have more details.

Search the Xilinx Answer Records to get more info.
 

ODELAY is only feasible for sub nanosecond delays, so it's not answering the question how to generate 20 ns delay.
What is the sensitivity list of the process?
Click to expand...
Synthesis doesn't care for sensitivity lists although the tool may warn about missing entries.

Consider that all internal signal transitions are caused by clock edges, delays can be easily created for multiples of the clock period, under circumstances also for a half period utilizing both edges.

What's the clk frequency in the post #1 code?
 

ODELAY is only feasible for sub nanosecond delays, so it's not answering the question how to generate 20 ns delay.
Click to expand...
If the OP instantiates only 1 ODELAY then yes. It was just an idea to get started.

The OP can instantiates multiple ODELAYs and try to see if he gets somewhere near to the desired value. All 64 taps of an ODELAY can be utilized. I don't remember the delay per tap for non-series 7 Xilinx devices, but a theoretical estimation can be done before actual implementation.
 

Just realized that the thread is referring to XC264 CPLD, no ODELAY features available at all.
 

FvM said:
Synthesis doesn't care for sensitivity lists although the tool may warn about missing entries.
Click to expand...

That is right, but in post #1 following assignments:
Code dot - [expand]
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clock_out <= tmp;
clock_out3 <= tmp3;

are beyond "if (clk'event and clk='1') then".
That is why I have asked about the sensitivity list to get to know what is the OP's intention (synchronous process? right now it isn't).
 

First, big thanks to everyone for comments.

Yes, it's XC2C64A chip.

I wanna to put hear my full code project, but I had a warning from moderator how to put a code, he sends me a link with instruction but link do not open



- - - Updated - - -

this my full code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
  
entity Clock_Divider is
port ( clk: in std_logic;
clock_out: out std_logic;
clock_out2: out std_logic);
end Clock_Divider;
  
architecture bhv of Clock_Divider is
  
signal count: integer:=0;
signal tmp : std_logic := '0';
 
signal tmp2 : std_logic := '0';
 
  
begin
 
process(clk)
 
begin
 
if (clk'event and clk='1') then
count <=count+1;
 
 
if (count = 1) then
tmp <= NOT tmp;
count <= 0;
 
end if;
 
tmp2 <= NOT tmp2;
 
end if;
 
clock_out <= tmp;
clock_out2 <= tmp2;
 
 
end process;
  
end bhv;


clk input 45Mhz
clock_out 22.5Mhz
Clock_out2 22.5Mhz

question again, how make clock_out or clock_out2 more late compare to each other, for example 20ns difference.
 

Hi,

CLK = 45mhz
Click to expand...
I think it should be MHz (Megahertz) instead of mHz (millihertz).

Then you may delay it for a complete clock cycle: it´s not 20ns but 22.22ns.

Then try this.
(I´m no specialist in this, and did not test it)


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
  
entity Clock_Divider is
port ( clk: in std_logic;
clock_out: out std_logic;
clock_out2: out std_logic);
end Clock_Divider;
  
architecture bhv of Clock_Divider is
  
signal count: integer:=0;
signal tmp : std_logic := '0';
 
signal tmp2 : std_logic := '0';
   
begin
 
    process(clk)
     
        begin
         
            if (clk'event and clk='1') then
                count <=count+1;
             
                if (count = 1) then
                    tmp <= NOT tmp;
                    count <= 0;
                end if;
             
                clock_out <= tmp;
                clock_out2 <= clock_out;
             
            end if;
         
    end process;
  
end bhv;
 

sorry, you must not understand what exactly need for me.
clk = 45158400Hz, but this not important at all. my divider is working properly. a question in another, how to make one from clock_outS output later compare to another.
I'm thinking before this simple task, and peoples with experience give me advise.
it's my first project if someone gives me exactly code I will be very appreciated
 

Hi,

I assume you didn´t try the code...(just complain about it?)

What are your results of the code of post#15?

Klaus
 

Just realized that the thread is referring to XC264 CPLD, no ODELAY features available at all.
Click to expand...
With that being said, I have no idea how to do it on a XC2C64A.
If it was a Xilinx 7 series FPGA, the chained IDELAY approach might have helped.
 

As explained in various posts, you have the option to implement Tclk and possibly 1/2 Tclk delay, should be sufficient for the intended purpose. Otherwise you'll either need to use a higher clock frequency or analog (RC or LC) delay elements, as people did in the good old times of discrete logic design.

Gate delays may supplement clock timed delay for fine tuning, but I would try to avoid it in a first order.
 

KlausST said:
Hi,

I assume you didn´t try the code...(just complain about it?)

What are your results of the code of post#15?

Klaus
Click to expand...

No, this does not work. I have the error when compiling:
Line 33. Object clock_out of mode OUT can not be read.

anyway, your proposal is only inverted signal probably.
20ns delay its only for example, but what we will do for delay 7 or 14ns?


dpaul said:
With that being said, I have no idea how to do it on a XC2C64A.
If it was a Xilinx 7 series FPGA, the chained IDELAY approach might have helped.
Click to expand...

I will be very appreciated if you give precisely chip number for ordering, where I will be the success with my target.
 

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