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Aske for help, about PNP in TSMC180nm technology

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pecroger

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Hi everyone,

I am working on my project by using TSMC180nm technology, and there is a PNP in my schematic, can I ask what's the meaning of the Device area? Is this the area of the emitter? Moreover, for the Layout, does anyone have a tutorial for PNP layout? I found an example from the CMCshare, but that is not what I want.
Please help.
Thanks for your time and have a beautiful day.
Sincerely,
Yisheng
 

You probably will not be allowed to make arbitrary layouts,
I tend to see one or two fixed geometry subPNP cells (if any).
The modeling task gets difficult as you add degrees of layout
freedom, and the subPNP is always a barely tolerated element
(everybody wants one for the bandgap, otherwise pretty
useless).

AREA= is -meant- to be emitter area but a fixed geometry
model may be fitted with AREA=1 for simplicity's sake (as
then params are straight-up from measured, not all needing
to be scaled by drawn dimensions (which won't change, so
why get fancy?).
 

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