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Top level IO cells connection (multiple IO voltages and global source use) and ESD

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NikosTS

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Top level IO cells connection ( multiple IO voltages and global source use ) and ESD

Hello everybody,
I want to connect the IO cells(pads) to the final schematic design. These cells according to the manual can be used for IO voltages of 1.8, 2.5 and 3.3V. Is there some way to make the design tool ( Cadence Virtuoso ) understand what voltage am i going to use? There are some global sources available at the IO cell library ( i.e TAVDD18, TAVDD25 , TAVDD33) but i havent figured out how to use them.

Again according to the manual, the ESD protection is embedded in these cells. So , i connect correctly the appropriate Power Clamp cell between the power and ground cells and test the clamping.
The stimulus is generated through a charged capacitor in series with a resistance , that discharges to an input pad. When i run a transient simulation, i should see the voltage of the input pad clamp the discharge to around 0V rather quickly ( a couple of us ) but it seems that it takes around 200ms (!). If i run it for only some us, i get a "steady" state at about 9V ( that will surely destroy the device ).

Any advice?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
Hello everybody,
I want to connect the IO cells(pads) to the final schematic design. These cells according to the manual can be used for IO voltages of 1.8, 2.5 and 3.3V. Is there some way to make the design tool ( Cadence Virtuoso ) understand what voltage am i going to use? There are some global sources available at the IO cell library ( i.e TAVDD18, TAVDD25 , TAVDD33) but i havent figured out how to use them.

Again according to the manual, the ESD protection is embedded in these cells. So , i connect correctly the appropriate Power Clamp cell between the power and ground cells and test the clamping.
The stimulus is generated through a charged capacitor in series with a resistance , that discharges to an input pad. When i run a transient simulation, i should see the voltage of the input pad clamp the discharge to around 0V rather quickly ( a couple of us ) but it seems that it takes around 200ms (!). If i run it for only some us, i get a "steady" state at about 9V ( that will surely destroy the device ).

Any advice?
Click to expand...

You can tell the simulator which voltage to use, just instantiate the power source with the voltage you want. Spectre is an electrical simulator, not an 'intent' simulator. Build the pad ring accordingly, read the manual carefully, and you will understand how to make it work for a given voltage.

I don't know the specifics of the IO library you are using, but usually there is nothing for you to connect by hand. You build the full ring with the RIGHT cells and it will work.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Hello,
I am trying to simulate HBM , and as far as i know during such an ESD event the power rail is floating (? ). The approach we will use will be Area-I/o flipchip so there will not be any pad ring.
Also the technology is TSMC 65nm

Thank you for your answer
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
Hello,
I am trying to simulate HBM , and as far as i know during such an ESD event the power rail is floating (? ). The approach we will use will be Area-I/o flipchip so there will not be any pad ring.
Also the technology is TSMC 65nm

Thank you for your answer
Click to expand...

If you are using Area IO, then ESD protection is up to you to design. The IO library manual still is the first place to start as they have recommendations and possibly a stand alone ESD cell that has to be used (not in ring fashion).
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

ThisIsNotSam said:
If you are using Area IO, then ESD protection is up to you to design. The IO library manual still is the first place to start as they have recommendations and possibly a stand alone ESD cell that has to be used (not in ring fashion).
Click to expand...


But according to the manual ESD protection is embedded in power/ground/IO cells, so why would ESD protection be up to me to design? I will just pop these cells around?
Unfortunatelly the IO library manual is pretty confusing.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
But according to the manual ESD protection is embedded in power/ground/IO cells, so why would ESD protection be up to me to design? I will just pop these cells around?
Unfortunatelly the IO library manual is pretty confusing.
Click to expand...

A portion of the ESD protection sits on the cell itself, of course. But the ESD protection scheme is only complete when the cells are abutted to form a rail. If using area IO, you don't have a rail. But you are still in charge of providing ESD protection beyond what the cell delivers.

TSMC manuals are known for being garbage. Good luck.
 
Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

ThisIsNotSam said:
A portion of the ESD protection sits on the cell itself, of course. But the ESD protection scheme is only complete when the cells are abutted to form a rail. If using area IO, you don't have a rail. But you are still in charge of providing ESD protection beyond what the cell delivers.

TSMC manuals are known for being garbage. Good luck.
Click to expand...

Well i understand , thank you! If the cell now has, lets say, double diode embedded would I need to add an appropriate size GGNMOS for instance? Or another pair of double diodes?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
Well i understand , thank you! If the cell now has, lets say, double diode embedded would I need to add an appropriate size GGNMOS for instance? Or another pair of double diodes?
Click to expand...

Maybe something is missing with the trigger part?

And yes for HBM analysis, the power rails have to be floating, but your netlist should have a 0 (ground) node in order to SPICE work successfully, and your circuit and the charge generator should be connected to same ground node.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

dr_kca said:
Maybe something is missing with the trigger part?

And yes for HBM analysis, the power rails have to be floating, but your netlist should have a 0 (ground) node in order to SPICE work successfully, and your circuit and the charge generator should be connected to same ground node.
Click to expand...

Thank you for you answer . I do have a ground (otherwise the simulator wont work indeed ) but i dont have a circuit . The input pad ( that should connect to a terminal of a device lets say ) is left floating and i am measuring the voltage at that node. It shouldnt make a difference if I left it floating or connect it to a device ( the simplest circuit ) right?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
Thank you for you answer . I do have a ground (otherwise the simulator wont work indeed ) but i dont have a circuit . The input pad ( that should connect to a terminal of a device lets say ) is left floating and i am measuring the voltage at that node. It shouldnt make a difference if I left it floating or connect it to a device ( the simplest circuit ) right?
Click to expand...

I don't understand your point, what do you mean by "i don't have a circuit" ? I assumed you have your PAD design that you are instantiated in a ESD HBM testbench in order to simulate the response.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

dr_kca said:
I don't understand your point, what do you mean by "i don't have a circuit" ? I assumed you have your PAD design that you are instantiated in a ESD HBM testbench in order to simulate the response.
Click to expand...

I mean that the PAD does not connect anywhere . The wire that should connect the PAD cell with the internal circuit is left floating and i measure the response of the testbench on that floating wire. It shouldnt make a difference if a left it floating or connect it to a e.g transistor gate right?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

I assume your "PAD" cell is your I/O block and you are just simulating ESD response of your I/O block, by discharging an ESD charge through the input/output pad (physical pad signal communicating with the external world). As far as I understood from your very first message, in your netlist you do also have power/ground cells, not just independent voltage sources. If this is the case, does your power/gnd cells have a lot of decoupling capacitors (and probably their own ESD circuitries) ? I think you are looking for reaching the "0V level" after the ESD is triggered. I remember simulating once upon in a time relatively "slow" discharging times to 0V when I use real power/ground cells in the netlist instead of just independent voltage sources, due to huge capacitance that has to charged/discharged. However, the pad voltage should go down below the allowed range much more quickly (few us). If the voltage level is in the allowed range within a short time, you can assume your circuit is protected.
 
Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

dr_kca said:
I assume your "PAD" cell is your I/O block and you are just simulating ESD response of your I/O block, by discharging an ESD charge through the input/output pad (physical pad signal communicating with the external world). As far as I understood from your very first message, in your netlist you do also have power/ground cells, not just independent voltage sources. If this is the case, does your power/gnd cells have a lot of decoupling capacitors (and probably their own ESD circuitries) ? I think you are looking for reaching the "0V level" after the ESD is triggered. I remember simulating once upon in a time relatively "slow" discharging times to 0V when I use real power/ground cells in the netlist instead of just independent voltage sources, due to huge capacitance that has to charged/discharged. However, the pad voltage should go down below the allowed range much more quickly (few us). If the voltage level is in the allowed range within a short time, you can assume your circuit is protected.
Click to expand...

You understood exactly what im trying to do. I do have power and ground cells as well, a power clamp between the power/ground rails and the I/O block on which im measuring the voltage after the "ESD event".
In most cases, the discharge quickly ( in about 10us ) reaches acceptable voltage level.In a single case ,which is a positive discharge between I/O cell ( input/output pad) and ground that should discharge through the power clamp, the voltage level is still pretty high after 10us and reaches acceptable level after 100 or more ms (!).
The power and ground cells have their own ESD circuitry but i dont see any capacitance. The power clamp also doesnt have a capacitor ( i assume it is not the standard RC -triggered ) but only a bunch of transistors and a couple of resistors.

Any ideas?

Thank you
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Are you sure that the devices that are used in the input/output ESD circuitry are simulable with your SPICE models (or maybe you are missing i library) ?
I don't know which CMOS techno/DK you are using but I once used a DK from a foundry in which GGNMOS device that is used in ESD IPs was not simulable with SPICE models, the lateral parasitic transistor was not modeled.

Otherwise I can' think about any other solution, assuming the design/layout is functioning.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Well due to CDB to OA conversion that i had to do, the schematic is messed up and i cant figure out the architecture of the cell. If there was a GGNMOS, it could explain the strange response. As far as i know ( and have read ) GGNMOS relies on snapback phenomenon which in most cases is not modelled ( correct me if i am wrong )
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

I know it's modeled in some DK for more recent nodes like 28nm for example, but 65nm it s not that "recent". So yes it is possible that it is not modeled but the only way to be sure is to contact TSMC support in your case.
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Thank you for your answers, maybe i should contact.
One last thing, i have noticed that if i connect a single test device ( e.g NMOS ) in the testbench then i get a proper discharge in all cases.
In that new testbench do be more exact, i connect the drain of NMOS to VDD rail , source to VSS rail and gate to IO cell. Then i discharge a pulse on the gate. In every combination between the input pin ( which is the gate of the NMOS ) and the VDD/VSS rail , the voltage reaches acceptable levels quickly.
Now, if i delete the test NMOS and get back to my old testbench, i still have problems with a discharge case.

Nothing else is changed on the testbench except the added test device.

Does that even make sense?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

ESD charge should not attack the gate of a MOS. Probably what is happening is that the MOS model behaves out of specification and for whatever reason and you see a discharge, which is a "false true". The discharge path should go through the drain/source of a MOS.
I think the best you can do is to contact the support.

Rgrds,
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

I will contact them, thank you.
BTW what do you mean by " should not attack the gate of a MOS "? If the input pad is connected to the gate of a MOS, the overvoltage should be seen at that terminal right?
 

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

NikosTS said:
I will contact them, thank you.
BTW what do you mean by " should not attack the gate of a MOS "? If the input pad is connected to the gate of a MOS, the overvoltage should be seen at that terminal right?
Click to expand...

In a bi-directional I/O pad design, I/O signal should go first through ESD protection before reaching any MOS gate, so that the MOS gate won't suffer any oxide breakdown. Therefore a signal which is not yet protected, should not be connected to any MOS gate. Maybe i misunderstood what you have described, but i thought that is what you did.

I am curious for the ESD device model question. Please update this post if you are given a useful answer.
 

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