Chaoping
Newbie level 4
How to optimize all transistors' size (length and width) in Cadence software?
For example, when I am designing a two stage differential single ended amplifier in 130nm. The minimum length and width are 120nm and 160nm. I just set the minimum size and adjust the multiple parameter in the global swiping. Does it right?
Thank you for all advises!
For example, when I am designing a two stage differential single ended amplifier in 130nm. The minimum length and width are 120nm and 160nm. I just set the minimum size and adjust the multiple parameter in the global swiping. Does it right?
Thank you for all advises!