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How to optimize all transistors' size (length and width) in Cadence software?

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Chaoping

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How to optimize all transistors' size (length and width) in Cadence software?
For example, when I am designing a two stage differential single ended amplifier in 130nm. The minimum length and width are 120nm and 160nm. I just set the minimum size and adjust the multiple parameter in the global swiping. Does it right?

Thank you for all advises!
 

All I know is "the hard way".

But there's always someone looking to sell you a tool.

Gone and bought the most expensive one and it comes up
short, I guess.

Parametric Analysis is half of a poor man's optimization
routine (a poor man with a nice computer and a hella
software budget, that is). The other half is said poor
man's intelligence and ability.
 

All I know is "the hard way".

But there's always someone looking to sell you a tool.

Gone and bought the most expensive one and it comes up
short, I guess.

Parametric Analysis is half of a poor man's optimization
routine (a poor man with a nice computer and a hella
software budget, that is). The other half is said poor
man's intelligence and ability.

As my understanding, there are two ways. One is computer automatic optimization. The other one is hand calculating + computer automatically optimization. But the devices model used in PDK is totally different from the well-known model. I.E, Hand calculating is waiting time, isn’t it? Why not let computer swiping all the parameters with the condition we have set?

Any comments?
 

I am sorry to say this but you should not. If you are unable to understand where to start a differential amplifier using hand calculations, you are not qualified to be an analogue design engineer. I know this is rude but what you say is a catastrophe.
 

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