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timing analysis with generated clocks

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stanford

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timing analysis with generated clks

Let's say you have clk1 with freq1 and clk2 is generated from clk1 and it is freq1/2 (div2 of clk1). How do we time paths between two posedge flops with clk1 and clk2?

1. For setup, the timing between the two should be done at clk1 right?
2. And for hold, do we do our regular hold analysis on the same clk edge and clk freq does not matter?
 

Re: timing analysis with generated clks

Setup should be done on capturing flop's clock. In this case, I am assuming that capturing flop is clocked by clk2 (div/2). Also think about skew if any.
Hold should be on same clk edge of clk2.
 

Re: timing analysis with generated clks

Setup should be done on capturing flop's clock. In this case, I am assuming that capturing flop is clocked by clk2 (div/2). Also think about skew if any.
Hold should be on same clk edge of clk2.

even if capturing flop is clk1, it still needs to be timed at freq1 right?
 

Re: timing analysis with generated clks

These two clocks should be analysed separately, i.e. setup and hold times for both clk1 and clk2, even if clk2 is generated from clk1.
Domain crossing between these two clock should be done by serialisers.
 

Re: timing analysis with generated clks

These two clocks should be analysed separately, i.e. setup and hold times for both clk1 and clk2, even if clk2 is generated from clk1.
Domain crossing between these two clock should be done by serialisers.

you need the STA tool to analyze all clocks and all possible clock1-to-clock2 paths, regardless of the presence of a serialiser.
 

Re: timing analysis with generated clks

Hi,

If possible, run all flip-flops with clk1 only. Don't create a second clock (clk2) but create an ENABLE signal instead.
Then all the setup and hold timing is related on clk1.

Klaus
 

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